OXCB950 datasheet(9/68 Pages) ETC

9 / 68 page

Data Sheet Revision 1.1

Page 9

OXCB950

OXFORD SEMICONDUCTOR LTD.

Multi-purpose & External

interrupt pins

Dir1

Name

Description

T_I/O

MIO[0]

MIO[1]

Multi-purpose I/O pins.

Can be driven high or low, or be used to invoke

cardbus/PCI interrupts, and powerdown, wakeup requests.

EEPROM pins

EE_CK

EEPROM clock

EE_CS

EEPROM active-high Chip Select

EE_DI

EEPROM data in (to be connected to the EEPROM DO

pin).

When the optional serial EEPROM is connected, this pin

should be pulled up using an external 1-10k resistor. When

the EEPROM is not used, this external pull-up is not

required (internal pull-up is sufficient).

EE_DO

EEPROM data out. (to be connected to the EEPROM DI

pin)

Miscellaneous pins

TEST0

Test Pin 0. Should be held low at all times.

TEST1

Test Pin 1. Should be held low at all times

Power and ground2

89, 14, 63

VDD3I_CB

Supplies power to the pre-drive area of the dual mode

cardbus/pci IO buffers.

56, 71, 81, 91, 7, 21

VDD3OP_CB

Supplies power to the output drive of the dual mode

cardbus/pci IO buffers.

38, 39

VDDIP

Supplies power to the core-logic and pre-drive area of the

standard IO buffers.

41,

VDDO

Suppiles power to the output drive of standard IO buffers.

62, 87, 13

VSSI_CB

Supplies ground to the pre-drive area of the dual mode

cardbus/pci IO buffers.

55, 64,65,70, 76, 82, 90, 92, 97,

2, 6, 12, 20,

VSSOP_CB

Supplies ground to the output drive of the dual mode

cardbus/pci IO buffers.

VSSIP

Supplies gnd to the core-logic and pre-drive area of the

standard IO buffers.

40, 50

VSSO

Supplies gnd to the output drive of standard IO buffers.

Table: Pin Descriptions

Note 1: Direction key:

3.3v Input, TTL compatible

3.3v Input with pull-down, TTL compatible

3.3v Input with pull-up, TTL compatible

3.3v Output, TTL compatible

T_O

5.0v tolerant TTL output

T_I

5.0v tolerant TTL input

T_I/O

5.0v tolerant TTL Bi-directional

C/P_I

Cardbus/PCI compatible input

C/P_O Cardbus/PCI compatible output

C/P_I/O Cardbus/PCI compatible bi-directional

C/P_OD Cardbus/PCI compatible open drain

Ground

3.3V power

Note 2: Power & Ground

There are several types of VDD and VSS in this design, providing not only power for the internal (core) and I/O pad area but also

special power lines to the dual mode cardbus/pci I/O buffers. These power rails are not connected internally.

This precaution reduces the effects of simultaneous switching outputs and undesirable RF radiation from the chip. Further

precaution is taken by segmenting the GND and VDD rails to isolate the PCI and UART pins.

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