OXCB950 datasheet(7/68 Pages) ETC

7 / 68 page

Data Sheet Revision 1.1

Page 7

OXCB950

OXFORD SEMICONDUCTOR LTD.

4 PIN DESCRIPTIONS

Cardbus/PCI bus Pins

Dir1

Name

Description

52, 53, 54, 57, 58, 60, 61, 66,

69, 73, 74, 75, 77, 78, 79, 100,

1, 3, 4, 5, 8, 9, 10, 11, 16, 17,

18, 19, 22, 23, 24, 25

C/P_I/O

AD[31:0]

Multiplexed Address/Data bus.

67, 80, 99, 15

C/P_I

C/BE[3:0]#

Multiplexed Command/Byte enable.

CP_I

CLK

System clock

CP_I

FRAME#

Cycle Frame1.

CP_O

DEVSEL#

Device Select

CP_I

IRDY#

Initiator ready

CP_O

TRDY#

Target ready

CP_O

STOP#

Target Stop request

CP_I/O

PAR

Parity

CP_O

SERR#

System error

CP_I/O

PERR#

Parity error

CP_I

IDSEL

Initialisation device select

For PCI applications this pin must be connected to the IDSEL

pin on the PCI connector. For cardbus applications, there is

no IDSEL signal, so this pin must be tied to Vdd (3.3v) via a

pull-up on the board. (10K recommended).

CP_I

RST#

System reset

CP_OD

INTA# /CINT#

Interrupt Pin. For both cardbus and pci applications

CP_O

CSYSCHG

Power management event signal, for Cardbus applications

This pin must be No-Connect (NC) for PCI applications.

CP_OD

PME#

Power management event signal, for PCI applications

This pin must be No-Connect (NC) for cardbus applications.

SLEW_RATE

Slew rate control for cardbus/pci outputs

For cardbus applications, this must be tied to Vdd on the

board. For PCI applications, this must be tied to Gnd on the

board.

For cardbus applications, the pin z_frame requires a pull-up (4k7) on the board. See PC Card Standard 7.0/7.1, section

5.3.3.3.3 “pull-up resistor requirements”.

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