ST10F166 datasheet(26/62 Pages) STMICROELECTRONICS

26 / 62 page

26/62

ST10F166

G.P.T. (Cont’d)

In addition to their basic operating modes, timers T2 and T4 may be configured as re-

load or capture registers for timer T3. When used as capture or reload registers, tim-

ers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in re-

sponse to a signal at their associated input pins (T2IN, T4IN). Timer T3 is reloaded

with the contents of T2 or T4 either by an external signal or by a selectable state tran-

sition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately re-

load T3 on opposite state transitions of T3OTL with the low and high times of a PWM

signal, this signal can be constantly generated without software intervention.

With its maximum resolution of 200 ns (@fosc = 40 MHz), the GPT2 module provides

precise event control and time measurement. It includes two timers (T5, T6) and a

capture/reload register (CAPREL). Both timers can independently count up or down,

clocked with an input clock which is derived from a programmable prescaler.

Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer

T6, which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5, or it may be output on a port pin

(T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the

CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The

CAPREL register may capture the contents of timer T5 based on an external signal

transition on the corresponding port pin (CAPIN), and timer T5 may optionally be

cleared after the same signal transition. This allows absolute time differences to be

measured or pulse multiplication to be performed without software overhead.

ST10F166 bảng dữ liệu(PDF) 26 Page - STMicroelectronics