ST10F166 datasheet(8/62 Pages) STMICROELECTRONICS

8 / 62 page

8/62

ST10F166

2 MEMORY ORGANIZATION

The memory space of the ST10F166 is configured in a Von Neumann architecture

which means that code memory, data memory, registers and I/O ports are organized

within the same linear address space which currently includes 256 Kbytes. The en-

tire memory space can be accessed bytewise or wordwise. Particular portions of the

on-chip memory have additionally been made directly bit addressable.

The ST10F166 contains 32 Kbytes of FLASH EPROM for code or constant data,

mapped in segment 0 or in segment 1 by software.

A large dual port RAM of 1 Kbyte is provided as a storage for user defined variables,

for the system stack, general purpose register banks and even for code. A register

bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, . . .,

RL7, RH7) called General Purpose Registers (GPRs).

512 bytes of the address space are reserved for the Special Function Register (SFR)

area. SFRs are registers which are used for controlling and monitoring functions of

the different on-chip units. 118 SFRs are currently implemented. Unused SFR ad-

dresses are reserved for future members of the ST10 Family.

In order to meet the needs of designs where more memory is required than is provid-

ed on chip, up to 256 Kbytes of external RAM and/or ROM can be connected to the

microcontroller.

ST10F166 bảng dữ liệu(PDF) 8 Page - STMicroelectronics