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28F032B3 bảng dữ liệu(PDF) 22 Page - Intel Corporation |
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28F032B3 bảng dữ liệu(HTML) 22 Page - Intel Corporation |
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22 / 48 page ![]() SMART 3 ADVANCED BOOT BLOCK E 22 PRELIMINARY After any program or block erase operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired. 3.7 Power Supply Decoupling Flash memory’s power switching characteristics require careful device decoupling. System designers should consider three supply current issues: 1. Standby current levels (ICCS) 2. Read current levels (ICCR) 3. Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. |
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