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MB95F856K bảng dữ liệu(PDF) 84 Page - Cypress Semiconductor |
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MB95F856K bảng dữ liệu(HTML) 84 Page - Cypress Semiconductor |
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84 / 172 page ![]() Document Number: 002-09305 Rev. *C Page 84 of 172 PRELIMINARY MB95F856K, MB95F866K, MB95F876K 14.2.3 Port 4 Port 4 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95850K/860K/870K Series Hardware Manual”. 1. Port 4 configuration ■ Port 4 is made up of the following elements. ❐ General-purpose I/O pins/peripheral function I/O pins ❐ Port 4 data register (PDR4) ❐ Port 4 direction register (DDR4) ❐ Port 4 pull-up register (PUL4) ❐ A/D input disable register (lower) (AIDRL) 2. Block diagrams of port 4 ■ P44/AN06/TO00/DIO03/PPG10 pin This pin has the following peripheral functions: ❐ 8/10-bit A/D converter analog input pin (AN06) ❐ 8/16-bit composite timer ch. 0 output pin (TO00) ❐ TS direct output ch. 3 pin (DIO03) ❐ 8/16-bit PPG ch. 1 output pin (PPG10) ■ P45/AN07/TO01/DIO04/PPG11 pin This pin has the following peripheral functions: ❐ 8/10-bit A/D converter analog input pin (AN07) ❐ 8/16-bit composite timer ch. 0 output pin (TO01) ❐ TS direct output ch. 4 pin (DIO04) ❐ 8/16-bit PPG ch. 1 output pin (PPG11) ■ Block diagram of P44/AN06/TO00/DIO03/PPG10 and P45/AN07/TO01/DIO04/PPG11 PDR4 Pin PDR4 read PDR4 write Executing bit manipulation instruction DDR4 read DDR4 write PUL4 read PUL4 write AIDRL read AIDRL write DDR4 PUL4 AIDRL 0 1 1 0 Stop mode, watch mode (SPL = 1) Peripheral function output enable Peripheral function output A/D analog input Hysteresis Pull-up |
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