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MB95F856K bảng dữ liệu(PDF) 5 Page - Cypress Semiconductor |
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MB95F856K bảng dữ liệu(HTML) 5 Page - Cypress Semiconductor |
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5 / 172 page ![]() Document Number: 002-09305 Rev. *C Page 5 of 172 PRELIMINARY MB95F856K, MB95F866K, MB95F876K Block Diagram (MB95870K Series) Reset with LVD Dual operation Flash with security function (36 Kbyte) F2MC-8FX CPU RAM (1 Kbyte) Oscillator circuit CR oscillator Clock control Watch prescaler Watch counter On-chip debug Wild register External interrupt ch. 0 to ch. 9 Interrupt controller 8/16-bit composite timer ch. 0 8/16-bit composite timer ch. 1 UART/SIO ch. 0 I2C bus interface ch. 0 8/16-bit PPG ch. 0 8/16-bit PPG ch. 2 Port Port PF2*1/RST*2 PF0/X0*2 PF1/X1*2 PG1/X0A*2 PG2/X1A*2 P00/INT00 to P05/INT05 P16/INT09 P17/INT08 P42*3/INT06 P43*3/INT07 C P13/UI0 P14/UO0 P15/UCK0 P40*3/PPG00 P41*3/PPG01 8/16-bit PPG ch. 1 (P42*3/PPG10) (P43*3/PPG11) P61/PPG20 P62/PPG21 8/10-bit A/D converter (P04/AN00) (P05/AN01) P06*3/AN02 P07*3/AN03 (P40*3/AN04) (P41*3/AN05) P44*3/AN06 P45*3/AN07 P47*1/SCL P46*1/SDA P10*1/DBG P11/EC0 (P44*3/TO00) (P45*3/TO01) (P16/TO11) (P17/TO10) P60/EC1 Comparator ch. 0 (P05/CMP0_N) (P06*3/CMP0_O) (P07*3/CMP0_P) Beep output unit P12/BEEP Touch sensor P64/S00 to P67/S03 P70/S04 to P77/S11 P63/AREF (P60/DIO00) (P11/DIO01) (P13/DIO02) (PG2/DIO03) (PG1/DIO04) (P44*3/DIO03) (P45*3/DIO04) Vcc Vss *1: P10, P46, P47 and PF2 are N-ch open drain pins. *2: Software select *3: P06, P07, and P40 to P45 are high-current pins. Note: Pins in parentheses indicate that those pins are shared among different peripheral functions. |
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