HT67F370 datasheet(23/225 Pages) HOLTEK

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HT67F370

TinyPowerTM A/D Flash MCU with LCD & EEPROM

HT67F370

TinyPowerTM A/D Flash MCU with LCD & EEPROM

System Architecture

Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedto

theirinternalsystemarchitecture.Therangeofthedevicetakeadvantageoftheusualfeaturesfound

withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.

Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction

executionareoverlapped,henceinstructionsareeffectivelyexecutedinoneortwocyclesformost

ofthestandardorextendedinstructionsrespectively.Theexceptionstothisarebranchorcall

instructionswhichneedonemorecycle.An8-bitwideALUisusedinpracticallyallinstructionset

operations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,

branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulator

andtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectly

orindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditional

architecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovidea

functionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthe

devicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and Pipelining

Themainsystemclock,derivedfromeitheraHXT,LXT,HIRCorLIRCoscillatorissubdivided

intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincremented

atthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.Theremaining

T2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clock

cycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplace

inconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthat

instructionsareeffectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructions

wherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhich

casetheinstructionwilltakeonemoreinstructioncycletoexecute.

Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twomachinecyclesare

requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone

cycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe

branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming

sensitiveapplications.

Fetch Inst. (PC+�)

Exec�te Inst. (PC+1)

Oscillato� Clock

(S�stem Clock)

Phase Clock T1

Phase Clock T�

Phase Clock T3

Phase Clock T4

P�og�am Co�nte�

Pipelining

PC+1

PC+�

Fetch Inst. (PC+1)

Exec�te Inst. (PC)

Exec�te Inst. (PC-1)

Fetch Inst. (PC)

System Clocking and Pipelining

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