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TDA8060ATS bảng dữ liệu(PDF) 11 Page - NXP Semiconductors |
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TDA8060ATS bảng dữ liệu(HTML) 11 Page - NXP Semiconductors |
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11 / 16 page ![]() This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... to PLL synthesizer IC Vtune from PLL synthesizer IC 100 nF FCE415 ASYM 100 nF 1 pF 100 nF AMP AMP SYM 1 pF LNA BASEBAND STAGE I CONVERTER × 100 MHz ASYM SYM Q CONVERTER × 100 MHz CONVERSION STAGE RFA 6 IBBOUT 13 QBBOUT to I channel ADC to Q channel ADC 12 VCC(BB) 9 BBGND 16 RFB RF (2) RF 5 AGC gain(1) 1 PEN 0 to 5 V 3 QUADRATURE GENERATOR STABILIZED LO PLL AND AMPLIFIER OSCILLATOR DIVIDE-BY-2 TDA8060ATS 10 QOUT 24 LOOUT 23 LOOUTC 19 TKA 20 TKB VCC(RF) 8 RFGND 7 VCC(MIX) 2 MIXGND 4 VCC(LO) 17 LOGND 18 VCC(DIV) 22 DIVGND 21 11 QBBIN IOUT 15 IBBIN 14 6 Ω 6 Ω 20 k Ω 20 k Ω 1 pF BB835 (2 ×) LOW-PASS FILTER(3) LOW-PASS FILTER(3) LOW-PASS FILTER(3) LOW-PASS FILTER(3) Fig.6 Application diagram. (1) Gain control voltage; minimum gain at 0.1VCC, maximum gain at 0.9VCC; 30 dB range. (2) Differential RF input 950 to 2200 MHz; level = −22 to −52 dBm per channel. (3) The filter input impedance is 400 Ω minimum. |
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