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TDA8060ATS bảng dữ liệu(PDF) 4 Page - NXP Semiconductors

tên linh kiện TDA8060ATS
Giải thích chi tiết về linh kiện  Satellite ZERO-IF QPSK down-converter
PDF  16 Pages
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nhà sản xuất  PHILIPS [NXP Semiconductors]
Trang chủ  http://www.nxp.com
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TDA8060ATS bảng dữ liệu(HTML) 4 Page - NXP Semiconductors

  TDA8060ATS Datasheet HTML 1Page - NXP Semiconductors TDA8060ATS Datasheet HTML 2Page - NXP Semiconductors TDA8060ATS Datasheet HTML 3Page - NXP Semiconductors TDA8060ATS Datasheet HTML 4Page - NXP Semiconductors TDA8060ATS Datasheet HTML 5Page - NXP Semiconductors TDA8060ATS Datasheet HTML 6Page - NXP Semiconductors TDA8060ATS Datasheet HTML 7Page - NXP Semiconductors TDA8060ATS Datasheet HTML 8Page - NXP Semiconductors TDA8060ATS Datasheet HTML 9Page - NXP Semiconductors Next Button
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2000 Nov 10
4
Philips Semiconductors
Product specification
Satellite ZERO-IF QPSK down-converter
TDA8060ATS
PINNING
SYMBOL
PIN
DESCRIPTION
AGC
1
RF amplifier gain control input
VCC(MIX)
2
supply voltage for mixer circuit (5 V)
PEN
3
prescaler enable
MIXGND
4
ground for mixer circuit
RFB
5
RF signal input B
RFA
6
RF signal input A
RFGND
7
ground for RF circuit
VCC(RF)
8
supply voltage for RF circuit (5 V)
VCC(BB)
9
supply voltage for baseband circuit
(5 V)
QOUT
10
‘Q’ output from demodulator
QBBIN
11
‘Q’ baseband amplifier input
QBBOUT
12
‘Q’ baseband amplifier output
IBBOUT
13
‘I’ baseband amplifier output
IBBIN
14
‘I’ baseband amplifier input
IOUT
15
‘I’ output from demodulator
BBGND
16
ground for baseband circuit
VCC(LO)
17
supply voltage for local oscillator
circuit (5 V)
LOGND
18
ground for local oscillator circuit
TKA
19
tank circuit input A
TKB
20
tank circuit input B
DIVGND
21
ground for divider circuit
VCC(DIV)
22
supply voltage for divider circuit
(5 V)
LOOUTC
23
local oscillator output to synthesizer
divided or not according to
PEN voltage
LOOUT
24
handbook, halfpage
TDA8060ATS
FCE412
1
2
3
4
5
6
7
8
9
10
11
12
AGC
VCC(MIX)
PEN
MIXGND
RFB
RFA
RFGND
VCC(RF)
VCC(BB)
QOUT
QBBIN
QBBOUT
LOOUT
LOOUTC
VCC(DIV)
DIVGND
TKB
TKA
LOGND
VCC(LO)
BBGND
IOUT
IBBIN
IBBOUT
24
23
22
21
20
19
18
17
16
15
14
13
Fig.2 Pin configuration.



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