ST68C554 datasheet(19/40 Pages) EXAR

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ST16C554/554D/68C554

Rev. 3.10

default condition)

Logic 1 = Enable the receiver ready interrupt.

IER BIT-1:

This interrupt will be issued whenever the THR is

empty and is associated with bit-1 in the LSR register.

Logic 0 = Disable the transmitter empty interrupt.

(normal default condition)

Logic 1 = Enable the transmitter empty interrupt.

IER BIT-2:

This interrupt will be issued whenever a fully as-

sembled receive character is transferred from the

RSR to the RHR/FIFO, i.e., data ready, LSR bit-0.

Logic 0 = Disable the receiver line status interrupt.

(normal default condition)

Logic 1 = Enable the receiver line status interrupt.

IER BIT-3:

Logic 0 = Disable the modem status register interrupt.

(normal default condition)

Logic 1 = Enable the modem status register interrupt.

IER BIT 4-7:

Not used - Initialized to a logic 0.

FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the

FIFOs, set the transmit/receive FIFO trigger levels,

and select the DMA mode. The DMA, and FIFO

modes are defined as follows:

DMA MODE

Mode 0

Set and enable the interrupt for each

single transmit or receive operation, and is similar to

the ST16C454 mode. Transmit Ready (-TXRDY) will

go to a logic 0 when ever an empty transmit space is

available in the Transmit Holding Register (THR).

Receive Ready (-RXRDY) will go to a logic 0 when-

ever the Receive Holding Register (RHR) is loaded

with a character.

Mode 1

Set and enable the interrupt in a block

mode operation. The transmit interrupt is set when the

transmit FIFO is below the programmed trigger level.

-TXRDY remains a logic 0 as long as one empty FIFO

location is available. The receive interrupt is set when

the receive FIFO fills to the programmed trigger level.

However the FIFO continues to fill regardless of the

programmed level until the FIFO is full. -RXRDY

remains a logic 0 as long as the FIFO fill level is above

the programmed trigger level.

FCR BIT-0:

Logic 0 = Disable the transmit and receive FIFO.

(normal default condition)

Logic 1 = Enable the transmit and receive FIFO. This

bit must be a 1 when other FCR bits are written to or

they will not be programmed.

FCR BIT-1:

Logic 0 = No FIFO receive reset. (normal default

condition)

Logic 1 = Clears the contents of the receive FIFO and

resets the FIFO counter logic (the receive shift regis-

ter is not cleared or altered). This bit will return to a

logic 0 after clearing the FIFO.

FCR BIT-2:

Logic 0 = No FIFO transmit reset. (normal default

condition)

Logic 1 = Clears the contents of the transmit FIFO and

resets the FIFO counter logic (the transmit shift regis-

ter is not cleared or altered). This bit will return to a

logic 0 after clearing the FIFO.

FCR BIT-3:

Logic 0 = Set DMA mode 0. (normal default condi-

tion)

Logic 1 = Set DMA mode 1.

Transmit operation in mode 0:

When the 554D is in the ST16C450 mode (FIFOs

disabled, FCR bit-0 = logic 0) or in the FIFO mode

(FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic

0) and when there are no characters in the transmit

FIFO or transmit holding register, the -TXRDY pin will

be a logic 0. Once active the -TXRDY pin will go to a

logic 1 after the first character is loaded into the

transmit holding register.

Receive operation in mode 0:

When the 554D is in mode 0 (FCR bit-0 = logic 0) or

in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =

logic 0) and there is at least one character in the

receive FIFO, the -RXRDY pin will be a logic 0. Once

active the -RXRDY pin will go to a logic 1 when there

are no more characters in the receiver.

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