ST68C554 datasheet(15/40 Pages) EXAR

15 / 40 page

ST16C554/554D/68C554

Rev. 3.10

DMA Operation

The 554D FIFO trigger level provides additional

flexibility to the user for block mode operation. LSR

bits 5-6 provide an indication when the transmitter is

empty or has an empty location(s). The user can

optionally operate the transmit and receive FIFOs in

the DMA mode (FCR bit-3). When the transmit and

receive FIFOs are enabled and the DMA mode is

deactivated (DMA Mode 0), the 554D activates the

interrupt output pin for each data transmit or receive

operation. When DMA mode is activated (DMA Mode

1), the user takes the advantage of block mode

operation by loading or unloading the FIFO in a block

sequence determined by the preset trigger level. In

this mode, the 554D sets the interrupt output pin when

characters in the transmit FIFOs are below the trans-

mit trigger level, or the characters in the receive FIFOs

are above the receive trigger level.

Loopback Mode

The internal loopback capability allows onboard diag-

nostics. In the loopback mode the normal modem

interface pins are disconnected and reconfigured for

loopback internally. MCR register bits 0-3 are used for

controlling loopback diagnostic testing. In the

loopback mode OP1 and OP2 in the MCR register

(bits 3/2) control the modem -RI and -CD inputs

respectively. MCR signals -DTR and -RTS (bits 0-1)

are used to control the modem -CTS and -DSR inputs

respectively. The transmitter output (TX) and the

receiver input (RX) are disconnected from their asso-

ciated interface pins, and instead are connected to-

gether internally (See Figure 12). The -CTS, -DSR, -

CD, and -RI are disconnected from their normal

modem control inputs pins, and instead are connected

internally to -DTR, -RTS, -OP1 and -OP2. Loopback

test data is entered into the transmit holding register

via the user data bus interface, D0-D7. The transmit

UART serializes the data and passes the serial data to

the receive UART via the internal loopback connec-

tion. The receive UART converts the serial data back

into parallel data that is then made available at the

user data interface, D0-D7. The user optionally com-

pares the received data to the initial transmitted data

for verifying error free operation of the UART TX/RX

circuits.

In this mode, the receiver and transmitter interrupts

are fully operational. The Modem Control Interrupts

are also operational. However, the interrupts can only

be read using lower four bits of the Modem Control

Status Register bits 4-7. The interrupts are still con-

trolled by the IER.

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