AD9675KBCZ datasheet(43/61 Pages) AD

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AD9675

Data Sheet

Rev. A | Page 42 of 60

DIGITAL BLOCK POWER SAVING SCHEME

To reduce power consumption in the digital block after the

ADC, the RF decimator and filter start in an idle state after

running the chip (Register 0x008, Bits[2:0] = 000). The digital

block only switches to a running state when the negative edge of

the TX_TRIG pulse is detected, or with a software TX_TRIG

write (Register 0x10C, Bit 5 = 1).

To put the digital block back into the idle state (while the rest of

the chip is still running) and to save power, enact one of the

following three events: raise the TX_TRIG signal high, write to

the profile index (Register 0x10C, Bits[0:4]), or the power stop

expires if the advanced power control feature is used. Figure 59

illustrates the digital block power saving scheme.

Figure 59. Digital Block Power Saving Scheme

CHIP IN POWER-DOWN,

STANDBY,

OR CW MODE

DIGITAL

DECIMATOR/FILTER

IDLE

DIGITAL

DECIMATOR/FILTER

RUNNING

RUN CHIP

NEGATIVE EDGE TX_TRIG

OR S/W TX_TRIG

TX_TRIG IS HIGH, PROFILE

INDEX WRITE, OR POWER

STOP EXPIRES

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