HT36A2 datasheet(8/24 Pages) HOLTEK

8 / 24 page

HT36A2

Rev. 1.00

June 19, 2003

cate the major 16 bits i.e. WA[15:5] and the undefined

data from WA[4~0] is always set to 00000b. So the start

address of each sample have to be located at a multiple

of 32. Otherwise, the sample will not be read out cor-

rectly because it has a wrong starting code.

Stack Register

- Stack

This is a special part of the memory which is used to

save the contents of the program counter (PC) only. The

stack is organized into 8 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At a subroutine call or interrupt acknowledgment, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a CALL is subse-

quently executed, a stack overflow occurs and the first

entry will be lost (only the most recent eight return ad-

dress are stored).

Data Memory

- RAM

The data memory is designed with 256

´ 8 bits. The data

memory is divided into three functional groups: special

function registers, wavetable function register, and gen-

eral purpose data memory (208

´8). Most of them are

read/write, but some are read only.

The special function registers include the Indirect Ad-

dressing register 0 (00H), the Memory Pointer register 0

(MP0;01H), the Indirect Addressing register 1 (02H), the

Memory Pointer register 1 (MP1;03H), the Accumulator

(ACC;05H), the Program Counter Lower-byte register

(PCL;06H), the Table Pointer (TBLP;07H), the Table

Higher-order byte register (TBLH;08H), the Watchdog

Timer option Setting register (WDTS;09H), the Status

(INTC;0BH), the Timer Counter 0 Lower-order byte reg-

ister (TMR0L;0DH), the Timer Counter 0 Control regis-

ter (TMR0C;0EH), the Timer Counter 1 Lower-order

byte register (TMR1L;10H), the Timer Counter 1 Control

PB;14H, PC;16H) and the I/O control registers

(PAC;13H, PBC;15H, PCC;17H). The program ROM

bank select (PF;1CH). The DAC High byte (DAH;1DH).

The DAC low byte (DAL;1EH). The DAC control

(DAC;1FH). The wavetable function registers is defined

between 20H~2AH. The remaining space before the

30H is reserved for future expanded usage and reading

these locations will return the result 00H. The general

purpose data memory, addressed from 30H to FFH, is

used for data and control information under instruction

command.

S p e c i a l P u r p o s e

D A T A M E M O R Y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

2 0 H

2 1 H

2 2 H

2 3 H

2 4 H

2 5 H

2 6 H

2 7 H

2 9 H

2 A H

2 B H

2 F H

F F H

: U n u s e d .

R e a d a s " 0 0 "

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M P 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M P 1

A C C

P C L

T B L P

T B L H

W D T S

S T A T U S

I N T C

T M R 0 L

T M R 0 C

T M R 1 L

T M R 1 C

P A

P A C

P B

P B C

P C

P C C

C h a n n e l n u m b e r s e l e c t

G e n e r a l P u r p o s e

D A T A M E M O R Y

( 2 0 8 B y t e s )

F r e q u e n c y n u m b e r h i g h b y t e

F r e q u e n c y n u m b e r l o w b y t e

S t a r t a d d r e s s h i g h b y t e

S t a r t a d d r e s s l o w b y t e

R e p e a t n u m b e r h i g h b y t e

R e p e a t n u m b e r l o w b y t e

V o l u m e c o n t r o l h i g h

2 8 H

3 0 H

W a v e t a b l e F u n c t i o n

R e g i s t e r

V o l u m c o n t r o l l o w

P F

D A C h i g h b y t e

D A C l o w b y t e

D A C c o n t r o l

RAM mapping

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