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SPEC-3093 (REV. 2)
4/15
29-09-2017
SA4305A
PIN DESCRIPTION
Designation
Pin No.
Description
AGND
16
Analog Ground. This is the reference pin for the current and voltage signal sensing
networks. The supply voltage to this pin should be mid-way between VDD and VSS.
VDD
6
Positive Supply Voltage. The voltage to this pin should be +2.5V ± 10% with respect to
AGND.
VSS
14
Negative Supply Voltage. The voltage to this pin should be -2.5V ± 10% with respect to
AGND.
IVP1, IVP2,
IVP3
17, 20, 3
Analog Inputs for Voltages. The maximum current into the voltage sense inputs IVP should
not exceed
16μARMS. At nominal voltage an input current of 14μARMS is recommended. The
voltage sense inputs saturate at an
input current of ±25μA peak.
IIP1, IIN1, IIP2,
IIN2, IIP3, IIN3
18, 19, 1, 2,
4, 5
Analog Inputs for Currents. The maximum current into the current sense inputs IIP/IIN
should be set at 16µARMS. The current sense inputs saturate at an input current of ±25µA
peak.
VREF
15
This pin provides the connection for the reference current setting resistor. A 47k
 resistor
connected to VSS sets the optimum operating conditions.
FOUT
8
Pulse output. Refer to the Pulse Output section for information on the pulse output
DIR
9
Direction Indicator output. This output indicates the direction of energy flow.
PGM0, PGM1
12, 13
Pulse Output Format Selection inputs. These input pins define the pulse output format.
Refer to the Pulse Output Format section for more information.
MS
11
Adder Mode Select input. Controls the mode of the pulse adder.
FPM
10
Fast Pulse Mode Select input. Controls the high frequency pulse output mode.
TEST
7
Manufacturers test pin. This pin should remain unconnected.
Figure 3: Pin connections
ORDERING INFORMATION
Part Number
Package
SA4305ASAR
SOIC20 (RoHS compliant)
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
IIP2
IIN2
IVP3
IIP3
IIN3
VDD
TEST
FOUT
IVP2
IIN1
IVP1
VREF
VSS
PGM1
9
10
12
11
DIR
FPM
PGM0
MS
IIP1
AGND



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