XT

July 1998

10

7.20.98

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Table 14: AC Timing Specifications, continued

data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are

± 3σ from typical.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

CLOCK

(MHz)

MIN.

TYP.

MAX.

UNITS

Clock Output (PCLK)

32.000

48

52

40.000

48

52

50.000

48

52

Duty Cycle *

From rising edge to rising edge at 2.5V

39.512

48

52

%

32.000

410

40.000

620

50.000

630

Jitter, Absolute (long term) *

Measured from rising edge to 1

edge after 0.1s at 2.5V;

39.512

620

ps

32.000

430

40.000

460

50.000

530

Jitter, Period *

Measured on the rising edges at 2.5V;

39.512

670

ps

Rise Time *

3.6

ns

Fall Time *

2.4

ns

Clock Stabilization *

Output active from power-up

400

µs

Clock Output (CLK27)

Duty Cycle *

Crystal oscillator frequency out, from rising

edge to rising edge at 2.5V

27

44

48

%

Clock Stabilization Time *

Output active from power-up

150

µs

Rise Time *

3.8

ns

Fall Time *

2.9

ns

Table 15: Serial Interface Timing Specifications

data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are

± 3σ from typical.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

MAX.

UNITS

SCLK clock frequency

0

100

kHz

Set up time, load

SLOAD

4.7

µs

Hold time, load

SLOAD

4.0

µs

Set up time, data

SDATA

250

ns

Hold time, data

SDATA

0

µs

Rise time

SDATA, SCLK

1000

ns

Fall time

SDATA, SCLK

300

ns

High time, serial clock

SCLK

4.0

µs

Low time, serial clock

SCLK

4.7

µs