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V850E/MA3 bảng dữ liệu(PDF) 72 Page - NEC

tên linh kiện V850E/MA3
Giải thích chi tiết về linh kiện  32-Bit Microprocessor Core
PDF  226 Pages
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CHAPTER 5 INSTRUCTIONS
User’s Manual U14559EJ3V1UM
72
<Arithmetic operation instruction>
Divide halfword
DIVH
Divide Halfword
Instruction format
(1) DIVH reg1, reg2
(2) DIVH reg1, reg2, reg3
Operation
(1) GR [reg2]
← GR [reg2] ÷ GR [reg1]
(2) GR [reg2]
← GR [reg2] ÷ GR [reg1]
GR [reg3]
← GR [reg2] % GR [reg1]
Format
(1) Format I
(2) Format XI
Opcode
15
0
(1)
rrrrr000010RRRRR
15
0
31
16
(2)
rrrrr111111RRRRR
wwwww01010000000
Flag
CY
–
OV
1 if overflow occurs; otherwise, 0.
S
1 if the result of an operation is negative; otherwise, 0.
Z
1 if the result of an operation is 0; otherwise, 0.
SAT
–
Explanation
(1) Divides the word data of general-purpose register reg2 by the lower halfword data of
general-purpose register reg1, and stores the quotient in general-purpose register reg2. If
the data is divided by 0, overflow occurs, and the quotient is undefined.
The data of
general-purpose register reg1 is not affected.
(2) Divides the word data of general-purpose register reg2 by the lower halfword data of
general-purpose register reg1, and stores the quotient in general-purpose register reg2
and the remainder in general-purpose register reg3. If the data is divided by 0, overflow
occurs, and the quotient is undefined. The data of general-purpose register reg1 is not
affected.
Remark
(1) The remainder is not stored.
Overflow occurs when the maximum negative value
(80000000H) is divided by –1 (in which case the quotient is 80000000H) and when data is
divided by 0 (in which case the quotient is undefined). If an interrupt occurs while this
instruction is being executed, execution is aborted, and the interrupt is serviced. Upon
returning from the interrupt, the execution is restarted from the beginning, with the return
address being the address of this instruction. Also, general-purpose registers reg1 and
reg2 will retain their original values prior to the start of execution.
Do not specify r0 as the destination register reg2.
The higher 16 bits of general-purpose register reg1 are ignored when division is executed.



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