V850ESLASHMA3 datasheet(70/226 Pages) NEC

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CHAPTER 5 INSTRUCTIONS

User’s Manual U14559EJ3V1UM

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SAT

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Explanation

(1) Adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to

word length, to sp. Then pops (loads data from the address specified by sp and adds 4 to

sp) the general-purpose registers listed in list12. Bit 0 of the address is masked by 0.

(2) Adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to

word length, to sp. Then pops (loads data from the address specified by sp and adds 4 to

sp) the general-purpose registers listed in list12, transfers control to the address specified

by general-purpose register reg1. Bit 0 of the address is masked by 0.

Remark

The general-purpose registers in list12 are loaded in the downward direction (r31, r30, ... r20).

The 5-bit immediate imm5 is used to restore a stack frame for auto variables and temporary

data.

The lower 2 bits of the address specified by sp are always masked by 0 even if misaligned

access is enabled.

If an interrupt occurs before updating sp, execution is aborted, and the interrupt is serviced.

Upon returning from the interrupt, the execution is restarted from the beginning, with the return

address being the address of this instruction (sp will retain its original value prior to the start of

execution).

Caution

If an interrupt is generated during instruction execution, due to manipulation of the stack, the

execution of that instruction may stop after the read/write cycle and register value rewriting are

complete. Execution is resumed after returning from the interrupt.

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