AD2S1200YST datasheet(18/25 Pages) AD

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AD2S1200

Rev. 0 | Page 17 of 24

Synthetic Reference Generation

When a resolver undergoes a high rotation rate, the RDC tends

to act as an electric motor and produces speed voltages, along

with the ideal Sin and Cos outputs. These speed voltages are in

quadrature to the main signal waveform. Moreover, nonzero

resistance in the resolver windings causes a non-zero phase shift

between the reference input and the Sin and Cos outputs. The

combination of speed voltages and phase shift causes a tracking

error in the RDC that is approximated by

Frequency

Reference

Rate

Rotation

Shift

Phase

Error

To compensate for the described phase error between the

resolver reference excitation and the Sin/Cos signals, an internal

synthetic reference signal is generated in phase with the refer-

ence frequency carrier. The synthetic reference is derived using

the internally filtered Sin and Cos signals. It is generated by

determining the zero crossing of either the Sin or Cos (which-

ever signal is larger, to improve phase accuracy) and evaluating

the phase of the resolver reference excitation. The synthetic

reference reduces the phase shift between the reference and

Sin/Cos inputs to less than 10°, and will operate for phase shifts

of ±45°.

SUPPLY SEQUENCING AND RESET

The AD2S1200 requires an external reset signal to hold the

RESET input low until VDD is within the specified operating

range of 4.5 V to 5.5 V.

The RESET pin must be held low for a minimum of 10 µs after

VDD is within the specified range (tRST in Figure 10). Applying a

RESET signal to the AD2S1200 initializes the output position to

a value of 0x000 (degrees output through the parallel, serial, and

encoder interfaces) and causes LOS to be indicated (LOT and

DOS pins pulled low) as shown in Figure 10.

Failure to apply the above (correct) power-up/reset sequence

can result in an incorrect position indication.

After a rising edge on the RESET input, the device must be

allowed at least 20 ms (tTRACK) as shown in Figure 10 for internal

circuitry to stabilize and the tracking loop to settle to the step

change in input position. After tTRACK, a SAMPLE pulse must be

applied, releasing the LOT and DOT pins to the state deter-

mined by the fault detection circuitry and providing valid

position data at the parallel and serial outputs (note that if

position data is being acquired via the encoder outputs, they

may be monitored during tTRACK).

The RESET pin is internally pulled up.

tRST

VDD

RESET

4.75V

VALID

OUTPUT

DATA

SAMPLE

LOT

DOS

tTRACK

Figure 10. Power Supply Sequencing and Reset

CHARGE PUMP OUTPUT

A 204.8 kHz square wave output with 50% duty cycle is avail-

able at the CPO output pin of the AD2S1200. This square wave

output can be used for negative rail voltage generation, or to

create a VCC rail.

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