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MFC2000 bảng dữ liệu(PDF) 165 Page - List of Unclassifed Manufacturers

tên linh kiện MFC2000
Giải thích chi tiết về linh kiện  Multifunctional Peripheral Controller 2000
PDF  426 Pages
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nhà sản xuất  ETC [List of Unclassifed Manufacturers]
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MFC2000 bảng dữ liệu(HTML) 165 Page - List of Unclassifed Manufacturers

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Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
100723A
Conexant
7-17
Bit 1-0
Transmit Mode[1:0]
Prior to writing to this register, check the ‘Send Status’ bit, and make sure that this bit is clear. If this bit is set,
then writing to this register will be ignored. If this bit is clear, then writing to this register will cause the following
action based on the ‘Transmit Mode’:
Transmit Mode
Time to send the serial data
0
right away
1
at the beginning of a scan cycle; no ‘scanonce’ operation is involved
2
at the end of valid pixel (i.e. the last valid pixel in a line); ‘scanonce’ operation is involved
3
at the next msint
Name/Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default
Scan Control
Delay
(ScanCtrlDelay)
$01FF88BD
sample
delay[1:0]
Scctrl[6]
Delay[1:0]
scctrl[5]
delay[1:0]
scctrl[4]
delay[1:0]
Rst. Value
xx000000b
Read Value
00h
Name/Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Scan Control
Delay
(ScanCtrlDelay)
$01FF88BC
scctrl[3]
delay[1:0]
Scctrl[2]
Delay[1:0]
scctrl[1]
delay[1:0]
clamp
delay[1:0]
Rst. Value
00h
Read Value
00h
Bit 15-14 sample delay
This setting controls the delay for ‘sample’ signal.
Bit 13-12 scctrl[6] delay
This setting controls the delay for ‘scctrl[6]’ signal.
Bit 11-10 scctrl[5] delay
This setting controls the delay for ‘scctrl[5]’ signal.
Bit 9-8
scctrl[4] delay
This setting controls the delay for ‘scctrl[4]’ signal.
Bit 7-6
scctrl[3] delay
This setting controls the delay for ‘scctrl[3]’ signal.
Bit 5-4
scctrl[2] delay
This setting controls the delay for ‘scctrl[2]’ signal.
Bit 3-2
scctrl[1] delay
This setting controls the delay for ‘scctrl[1]’ signal.
Bit 1-0
clamp delay
This setting controls the delay for ‘clamp’ signal.
Name/Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default
ADC Config
(ADCConfig)
$01FF88BF
AdclkNeg Value (0-15)
AdclkPos Value (0-15)
Rst. Value
00h
Read Value
00h
Name/Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
ADC Config
(ADCConfig)
$01FF88BE
Digital Data Capture Position [3:0] (0-15)
Data Latency[3:0] (0-15)
Rst. Value
00h
Read Value
00h



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