MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33879

9

DIGITAL INTERFACE TIMING (Note 14)

Recommended Frequency of SPI Operation (Note 14)

–4.0

–

MHz

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)

100

–

–

ns

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)

50

–

–

ns

DI to Falling Edge of SCLK (Required Setup Time)

16

–

–

ns

Falling Edge of SCLK to DI (Required Hold Time)

20

–

–

ns

DI, CS, SCLK Signal Rise Time (Note 15)

–5.0

–

ns

DI, CS, SCLK Signal Fall Time (Note 15)

–5.0

–

ns

Time from Falling Edge of CS to DO Low Impedance (Note 16)

–

–

55

ns

Time from Rising Edge of CS to DO High Impedance (Note 17)

–

–

55

ns

Time from Rising Edge of SCLK to DO Data Valid (Note 18)

–25

55

ns

Notes

14.

This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5V/3.1V SPI interface.

15.

Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

16.

Time required for output status data to be available for use at DO pin.

17.

Time required for output status data to be terminated at DO pin

18.

Time required to obtain valid data out from DO following the rise of SCLK.

DYNAMIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions of 3.1 V

Characteristic

Symbol

Min

Typ

Max

Units

Freescale Semiconductor, Inc.

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