AD9736BBC datasheet(30/42 Pages) AD

30 / 42 page

AD9736/AD9735/AD9734

Preliminary Technical Data

Rev. PrJ | Page 30 of 42

APPLICATIONS INFORMATION

FPGA/ASIC DAC DRIVER REQUIREMENTS

To achieve data synchronization using the high speed capability of

the AD9736, ADI recommends the configuration in Figure 35 for

the FPGA/ASIC driving the digital inputs. Using the Double Data

Rate DATACLK_OUT, this configuration will generate the LVDS

DATACLK_IN to drive the AD9736 at the DDR rate. The circuit

also synchronizes the DATACLK_IN and the digital input data

(DB<13:0>) as required by the AD9736. The synchronization

engine in the AD9736 then uses DATACLK_IN to generate the

internal CLOCK SAMPLING SIGNAL to capture the incoming

data via the Manual, Surveillance or Auto mode.

To operate in 2x mode, the circuit in Figure 35 must be modified to

include a divide-by-two block in the DATACLK_OUT path.

Without this additional divider the DATA and DATACLK_IN will

be running 2x too fast. DATACLK_OUT is always DACCLK/2.

Figure 35. Recommended FPGA/ASIC Configuration for Driving AD9736

Digital Inputs, 1x Mode

Figure 36. FPGA/ASIC Timing for Driving AD9736 Digital Inputs, 1x Mode

TIMING ERROR BUDGET

The following components make up the timing error budget for the

AD9736:

AD9736 DATACLK_OUT jitter

AD9736 DATACLK_IN jitter

DB13:0 jitter

DB13:0 skew from data source

DB13:0 receiver skew margin (board + AD9736 internal

delays)

DB13:0 to DATACLK_IN skew from data source

DATACLK_OUT+

DATA1

DATA2

DATACLK_IN+

AD9736BBC bảng dữ liệu(PDF) 30 Page - Analog Devices