AD7152 datasheet(4/24 Pages) AD

4 / 24 page

AD7152/AD7153

Data Sheet

Rev. A | Page 4 of 24

Parameter

Min

Typ

Max

Unit1

Test Conditions/Comments

POWER REQUIREMENTS

VDD-to-GND Voltage

2.7

3.6

VDD = 3.3 V, nominal

Current, IDD9

100

120

µA

Current Power-Down Mode, IDD9

µA

Temperature ≤ 25°C

µA

Temperature = 85°C

Capacitance units: 1 pF = 10−12 F; 1 fF = 10−15 F; 1 aF = 10−18 F.

Specification is not production tested but is supported by characterization data at initial product release.

Except Channel 2 in differential mode. To achieve the specified performance in differential mode, the I2C interface must be idle during the capacitance conversion to

prevent signal coupling from the SCL pin to the adjacent CIN2(−) pin.

Factory calibrated. The absolute error includes factory gain calibration error and integral nonlinearity error all at 25°C. At different temperatures, compensation for

gain drift over temperature is required.

Specification is not production tested but guaranteed by design.

A system offset calibration is effectively a conversion; therefore, the offset error is of the order of the conversion noise. This applies after calibration at the temperature,

capacitive input range, and applied VDD of interest. The capacitive input offset can be reduced using a system offset calibration. Large offsets should be removed using

CAPDACs.

The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.

The CAPDAC resolution is five bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can

further reduce the CIN offset or the unchanging CIN component.

Digital inputs equal to VDD or GND.

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