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AD9684 bảng dữ liệu(PDF) 44 Page - Analog Devices |
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AD9684 bảng dữ liệu(HTML) 44 Page - Analog Devices |
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44 / 65 page ![]() Data Sheet AD9684 LOW-PASS FILTER 2 I Q REAL HB1 FIR LOW-PASS FILTER 2 HB1 FIR 0 1 COMPLEX TO REAL ENABLE Q 90° 0° + – COMPLEX TO REAL CONVERSION I Q I Q GAIN STAGE cos(wt) sin(wt) fS/4 I/REAL 0dB OR 6dB 0dB OR 6dB 0dB OR 6dB 0dB OR 6dB Figure 66. Complex to Real Conversion Block DDC EXAMPLE CONFIGURATIONS Table 22 describes the register settings for multiple DDC example configurations. Table 22. DDC Example Configurations Chip Application Layer Chip Decimation Ratio DDC Input Type DDC Output Type Bandwidth Per DDC1 Number of Virtual Converters Required (M) Register Settings2 One DDC 2 Complex Complex 77% × fS 2 Register 0x200 = 0x01 (one DDC, I/Q selected) Register 0x201 = 0x01 (chip decimate by 2) Register 0x310 = 0x83 (complex mixer, 0 dB gain, variable IF, complex outputs, HB1 filter) Register 0x311 = 0x04 (DDC I input = ADC Channel A, DDC Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Two DDCs 4 Complex Complex 38.5% × fS 4 Register 0x200 = 0x02 (two DDCs, I/Q selected) Register 0x201 = 0x02 (chip decimate by 4) Register 0x310, Register 0x330 = 0x80 (complex mixer, 0 dB gain, variable IF, complex outputs, HB2 + HB1 filters) Register 0x311, Register 0x331 = 0x04 (DDC I input = ADC Channel A, DDC Q input = ADC Channel B) Rev. 0 | Page 43 of 64 |
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