AD7771BCPZ datasheet(13/99 Pages) AD

13 / 99 page

AD7771

Data Sheet

Rev. 0 | Page 12 of 98

SAR ADC TIMING CHARACTERISTISTICS

AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V;

IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX,

unless otherwise noted.

Table 5.

Parameter

Description2

Min

Typ

Max

Unit

t32

Conversion time

3.4

µs

t33

Acquisition time3

500

t34

Delay time

t35

Throughput data rate

256

kSPS

AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3 and AVSS4. This term is used throughout the data sheet.

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.

Direct mode enabled. If deglitch mode is enabled, add 1.5/MCLK as described in Table 29.

CONVST_SAR

t33

t32

t35

t34

Figure 5. SAR ADC Timing Diagram

GPIO SRC UPDATE TIMING CHARACTERISTISTICS

AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V;

IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications TMIN to TMAX,

unless otherwise noted.

Table 6.

Parameter

Description2

Min

Typ

Max

Unit

t36

GPIO2 setup time

t37

GPIO2 hold time—high resolution mode

MCLK

GPIO2 hold time—low power mode

2 × MCLK

t38

MCLK rising edge to GPIO1 rising edge time

t39

GPIO0 setup time

t40

GPIO0 hold time

MCLK

AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3 and AVSS4. This term is used throughout the data sheet.

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.

MCLK

GPIO2

GPIO1

GPIO0

t36

t37

t38

t39

t40

Figure 6. GPIOs for SRC Update Timing Diagram

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