LTC1850CFW datasheet(17/28 Pages) LINER

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LTC1850/LTC1851

18501f

the offset applied to the “–” input. For single-ended inputs,

this offset should be applied to the COM pin. For differen-

tial inputs, the “–” input is dictated by the MUX address.

For zero offset error, apply 0.5LSB (actual voltage will vary

with input span selected) to the “+” input and adjust the

offset at the “–” input until the output code flickers

between 0000 0000 0000 and 0000 0000 0001 for the

LTC1851 and between 00 0000 0000 and 00 0000 0001 for

the LTC1850.

As mentioned earlier, the internal reference is factory

trimmed to 2.500V. To make sure that the reference buffer

gain is not compensating for trim errors in the reference,

REFCOMP is trimmed to 4.096V with an accurate external

2.5V reference applied to REFIN. Likewise, to make sure

that the full-scale gain trim is not compensating for errors

in the reference buffer gain, the input full-scale gain is

trimmed with an accurate 4.096V reference applied to

REFCOMP (REFIN = 5V to disable the reference buffer).

This allows the use of either a 2.5V reference applied to

REFIN or a 4.096V reference applied to REFCOMP to

achieve accurate results. Full-scale errors can be trimmed

to zero by adjusting the appropriate reference voltage. For

unipolar inputs, an input voltage of FS – 1.5LSBs should

be applied to the “+” input and the appropriate reference

adjusted until the output code flickers between 1111 1111

1110 and 1111 1111 1111 for the LTC1851 and between

11 1111 1110 and 11 1111 1111 for the LTC1850.

For bipolar inputs, an input voltage of FS – 1.5LSBs should

be applied to the “+” input and the appropriate reference

adjusted until the output code flickers between 0111 1111

1110 and 0111 1111 1111 for the LTC1851 and between

01 1111 1110 and 01 1111 1111 for the LTC1850.

These adjustments as well as the factory trims affect all

channels. The channel-to-channel offset and gain error

matching are guaranteed by design to meet the specifica-

tions in the Converter Characteristics table.

APPLICATIO S I FOR ATIO

OUTPUT DATA FORMAT

The LTC1850/LTC1851 have a 14-bit/16-bit parallel out-

put. The output word normally consists of a 10-bit/12-bit

conversion result data word and a 4-bit address (three

address bits A2OUT, A1OUT, A0OUT and the DIFFOUT bit).

The output drivers are enabled when RD is low provided

the chip is selected (CS is low). All 14/16 data output pins

and BUSY are supplied by OVDD and OGND to allow easy

interface to 3V or 5V digital logic.

The data format of the conversion result is automatically

selected and determined by the UNI/BIP input pin. If the

UNI/BIP pin is low indicating a unipolar input span

(0 – REFCOMP assuming PGA = 1), the format for the

data is straight binary with 1 LSB = FS/4096 (1mV for

REFCOMP = 4.096V) for the LTC1851 and 1LSB = FS/

1024 (4mV for REFCOMP = 4.096V) for the LTC1850.

If the UNI/BIP pin is high indicating a bipolar input span

(

±REFCOMP/2 for PGA = 1), the format for the data is

two’s complement binary with 1 LSB = [(+FS) – (– FS)]/

4096 (1mV for REFCOMP = 4.096V) for the LTC1851 and

1LSB = [(+FS) – (– FS)]/1024 (4mV for REFCOMP =

4.096V) for the LTC1850.

In both cases, the code transitions occur midway between

successive integer LSB values (i.e., – FS + 0.5LSB,

– FS + 1.5LSB, ... – 1.5LSB, – 0.5LSB, 0.5LSB, 1.5LSB, ...

FS – 1.5LSB, FS – 0.5LSB).

The three most significant bits of the data word (D11,

D10, and D9 for the LTC1851; D9, D8 and D7 for the

LTC1850) also function as output bits when reading the

contents of the programmable sequencer. During

readback, a 7-bit status word (S6-S0) containing the

contents of the current sequencer location is available

when RD is low. The individual bits of the status word are

outlined in Figure 1. During readback, the D8 to D0 pins

(LTC1851) or D6 to D0 pins (LTC1850) remain high

impedance irrespective of the state of RD.

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