CS5471

6

±10%; DGND = AGND = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50pF))

Notes: 12. Device parameters are specified with a 4.000 MHz clock, OWRS = 1.

13. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

(Note 12)

XIN

3

4.000

5

MHz

Master Clock Duty Cycle

-

40

-

60

%

Rise Times

Any Digital Input (Note 13)

Any Digital Output

-

-

-

50

1.0

-

µs

ns

Fall Times

Any Digital Input (Note 13)

Any Digital Output

-

-

-

50

1.0

-

µs

ns

Serial Port Timing

Serial Clock Frequency

(Note 12)

OWRS = “0”

OWRS = “1”

SCLK

SCLK

-

-

500

1000

-

-

kHz

kHz

Serial Clock

Pulse Width High (Note 12)

Pulse Width Low (Note 12)

-

-

0.5

0.5

-

-

SCLK

SCLK

SCLK falling to New Data Bit

-

-

50

ns

FSO Falling to SCLK Rising Delay

(Note 12)

-0.5

-

SCLK

FSO Pulse Width

(Note 12)

-1

-

SCLK

SE Rising to Output Enabled

-

-

50

ns

SE Falling to Output in Tri-state

-

-

50

ns

SE

6

t

6

t

SDO

SCLK

t

2

t

1

t

3

FSO

4

t

5

t

MSB(V1)

MSB(V1) - 1

LSB(I2)

Figure 1. Serial Port Timing