WM8602SEDSSLASHV datasheet(19/46 Pages) WOLFSON

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WM8602

PP Rev 1.5 May 2004

MASTER CLOCK AND AUDIO SAMPLE RATES

The WM8602 supports a wide range of master clock frequencies on the MCLK pin, and can generate

many commonly used audio sample rates directly from the master clock. (See Table 14 for details.)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CMAST

Master Clock Mode

0 = MCLK input

1 = XIN input

MPEG

MPEG Mode

0 = see Table 14

1 = MCLK is 27MHz

MEDGE

Master Clock Active Edge

0 = positive edge

1 = negative edge

R0 (00h)

Clocking

CLKDIV2

Master Clock Divide by 2

1 = MCLK is divided by 2

0 = MCLK is not divided

Table 12 Clocking and Sample Rate Control (1)

If the WM8602 is running in MPEG mode (i.e. fXIN = 27MHz) the sample can be detected

automatically if the SRDET bit is set. In this case, the SR bits do not need programming.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:0

SR [3:0]

0000

Sample Rate Control. Refer to

Table 14.

R1 (01h)

Sample Rate

SRDET

Sample rate detect

1 = Enabled

(in MPEG mode only)

0 = Disabled

Table 13 Clocking and Sample Rate Control (2)

The clocking of the WM8602 is controlled using the CLKDIV2 and SR control bits. Setting the

CLKDIV2 bit divides MCLK by two internally. Each value of SR[3:0] selects one combination of

MCLK division ratios and hence one combination of sample rates (see next page). Since all sample

rates are generated by dividing MCLK, their accuracy depends on the accuracy of MCLK. If MCLK

changes the sample rates change proportionally.

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