MPC7457EC datasheet(61/68 Pages) FREESCALE

61 / 68 page

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

Document Revision History

10 Document Revision History

Table 22 provides a revision history for this hardware specification.

Table 22. Document Revision History

Revision

Number

Date

Substantive Change(s)

09/09/2004

Updated document to new Freescale template.

Updated section numbering and changed reference from part number specifications to addendums.

Added Rev. 1.2 devices, including increased L3 clock max frequency to 250 MHz and improved L3

AC timing.

Table 5: Added CTE information.

Table 8: Modified jitter specifications to conform to JEDEC standards, changed jitter specification to

cycle-to-cycle jitter (instead of long- and short-term jitter); changed jitter bandwidth

recommendations.

Table 13: Deleted note 9 and renumbered.

Table 14: Deleted note 5 and renumbered.

Table 17: Revised note 6.

Added Section 9.1.3.

Section 9.2: Changed filter resistor recommendations. Recommend 10

Ω resistor for all production

devices, including production Rev. 1.1 devices. 400

Ω resistor needed only for early Rev. 1.1

devices.

Table 22: Reversed the order of revision numbers.

Added Tables 25 and 26.

4.1

Section 9.1.1: Corrected note regarding different PLL configurations for earlier devices; all

MPC7457 devices to date conform to this table.

Section 9.6: Added information about unused L3_ADDR signals.

Table 24: Changed title to include document order information for MPC74x7RXnnnnNx series part

number specification.

Table 9: Corrected pin lists for input and output AC timing to correctly show HIT as an output-only

signal

Added specifications for 1267 MHz devices; removed specs for 1300 MHz devices.

Section 5.2.3: Changed recommendations regarding use of L3 clock jitter in AC timing analysis. The

L3 jitter is now fully comprehended in the AC timing specs and does not need to be included in the

timing analysis.

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