MPC7450EC datasheet(43/52 Pages) MOTOROLA

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MOTOROLA

MPC7450 RISC Microprocessor Hardware Speciﬁcations

System Design Information

Figure 23. JTAG Interface Connection

1.9.9

Thermal Management Information

This section provides thermal management information for the ceramic ball grid array (CBGA) package for

air-cooled applications. Proper thermal control design is primarily dependent on the system-level

design—the heat sink, airﬂow, and thermal interface material. To reduce the die-junction temperature, heat

HRESET

From Target

Board Sources

HRESET

SRESET

VDD_SENSE

2 k

Ω

10 k

Ω

10 k

Ω

10 k

Ω

OVDD

CHKSTP_IN

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

TRST

(if any)

142

Key

Notes:

1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7450.

Connect pin 5 of the COP header to OVDD with a 10 KΩ pull-up resistor.

2. Key location; Pin 14 is not physically present on the COP header.

QACK

OVDD

10 k

Ω

OVDD

2 k

Ω3

GND

3. Component not populated. Populate only if JTAG interface is unused.

TRST

10 k

Ω

OVDD

10 k

Ω

10 k

Ω

QACK

2 k

Ω4

QACK

CHKSTP_OUT

KEY

No pin

COP Connector

Physical Pin Out

4. Component not populated. Populate only if debug tool does not drive QACK.

10 k

Ω5

OVDD

5. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.

2 k

Ω4

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

INC

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