SC16C754 datasheet(8/49 Pages) PHILIPS

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Philips Semiconductors

SC16C754

Quad UART with 64-byte FIFO

Product data

Rev. 04 — 19 June 2003

8 of 49

9397 750 11618

Functional description

The SC16C754 UART is pin-compatible with the SC16C554 and SC16C654 UARTs.

It provides more enhanced features. All additional features are provided through a

special enhanced feature register.

The UART will perform serial-to-parallel conversion on data characters received from

peripheral devices or modems, and parallel-to-parallel conversion on data characters

transmitted by the processor. The complete status of each channel of the SC16C754

UART can be read at any time during functional operation by the processor.

The SC16C754 can be placed in an alternate mode (FIFO mode) relieving the

processor of excessive software overhead by buffering received/transmitted

characters. Both the receiver and transmitter FIFOs can store up to 64 bytes

(including three additional bits of error status per byte for the receiver FIFO) and have

selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow

signalling of DMA transfers.

The SC16C754 has selectable hardware ﬂow control and software ﬂow control.

Hardware ﬂow control signiﬁcantly reduces software overhead and increases system

efﬁciency by automatically controlling serial data ﬂow using the RTS output and CTS

input signals. Software ﬂow control automatically controls data ﬂow by using

programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing

reference clock input by a divisor between 1 and (216

− 1).

6.1 Trigger levels

The SC16C754 provides independent selectable and programmable trigger levels for

both receiver and transmitter DMA and interrupt generation. After reset, both

transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the

default value of one byte. The selectable trigger levels are available via the FCR. The

programmable trigger levels are available via the TLR.

6.2 Hardware ﬂow control

Hardware ﬂow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and

Auto-RTS can be enabled/disabled independently by programming EFR[7:6].

VCC

6, 46, 66 13, 47,

Power supply input.

XTAL1

Crystal or external clock input. Functions as a crystal input or as an

external clock input. A crystal can be connected between XTAL1 and XTAL2

to form an internal oscillator circuit (see Figure 13). Alternatively, an

external clock can be connected to this pin to provide custom data rates.

XTAL2

Output of the crystal oscillator or buffered clock. (See also XTAL1.)

XTAL2 is used as a crystal oscillator output or a buffered clock output.

Table 2:

Pin description…continued

Symbol

Type

Description

LQFP80 PLCC68

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