ADCS9888 datasheet(29/34 Pages) NSC

29 / 34 page

Application Information (Continued)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

100110

6.2.5 Register Address BYTE

ADCS9888 register addresses are an 8 bit value. Please

refer to the Register Address table at the beginning of the

datasheet for more detailed information.

6.2.6 Serial Interface Timeout

The serial interface incorporates a timeout feature. This is

present to ensure that the bus cannot become ‘locked’ if the

master and slave become out of sync due to noise or other

system issues.

An internal timer is used to guarantee that the interface is

reset if the SCL line is held low. This is used to prevent

problems in the case where the ADCS9888 is driving a low

on the SDA line and the master device is reset. This allows

the master to reset the state of the serial interface on the

ADCS9888 by simply driving a low on SCL for more than 50

ms.

The serial bus interface circuitry will be reset to the idle state

if the SCL line is held low for more than 50 ms. The bus may

be reset to idle if the SCL line is held low from 25 to 50 ms.

The bus will not be reset if the SCL line is held low for less

than 25 ms.

6.3 Specific Types Of Transfers

6.3.1 Write to Single Register

•

Start Signal

•

Slave Address Byte (R/W Bit = 0)

•

Data Byte to Register

•

Stop Signal

6.3.2 Burst Write to Multiple (3) Registers

•

Start Signal

•

Slave Address Byte (R/W Bit = 0)

•

Data Byte to Register

•

Data Byte to Register+1

•

Data Byte to Register+2

•

Stop Signal

6.3.3 Read from Single Register

•

Start Signal

•

Slave Address Byte (R/W Bit = 0)

•

Start Signal

•

Slave Address Byte (R/W Bit = 1)

•

Data Byte to Register

•

Stop Signal

6.3.4 Read from Multiple (3) Registers

•

Start Signal

•

Slave Address Byte (R/W Bit = 0)

•

Start Signal

•

Slave Address Byte (R/W Bit = 1)

•

Data Byte to Register

•

Data Byte to Register+1

•

Data Byte to Register+2

•

Stop Signal

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