56F8322 datasheet(70/136 Pages) MOTOROLA

70 / 136 page

56F8322 Techncial Data, Rev. 10.0

Freescale Semiconductor

Preliminary

5.6.10.5

ADC A Zero Crossing or Limit Error Interrupt Priority Level

(ADCA_ZC IPL)—Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.10.6

Reserved—Bits 5–4

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.10.7

ADC A Conversion Complete Interrupt Priority Level

(ADCA_CC IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.10.8

Reserved—Bits 1–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.11

Vector Base Address Register (VBA)

Figure 5-13 Vector Base Address Register (VBA)

5.6.11.1

Reserved—Bits 15–13

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.11.2

Interrupt Vector Base Address (VECTOR BASE ADDRESS)—

Bits 12–0

The contents of this register determine the location of the Vector Address Table. The value in this register

is used as the upper 13 bits of the interrupt vector address. The lower eight bits of the ISR address are

determined based upon the highest-priority interrupt; see Section 5.3.1 for details.

Base + $A

Read

VECTOR BASE ADDRESS

Write

RESET

00000000

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