RT8092

10

DS8092-03

January 2017

www.richtek.com

©

Copyright

2017 Richtek Technology Corporation. All rights reserved.

is a registered trademark of Richtek Technology Corporation.

Note 1. Stresses beyond those listed

“Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

SDA, SCL Input

Voltage

High-Level

1.2

--

--

V

Low-Level

--

--

0.4

Fast Mode

SCL Clock Rate

--

--

400

kHz

Hold Time (Repeated) START

Condition.

After this Period, the First Clock

Pulse is Generated

0.6

--

--

s

LOW Period of the SCL Clock

1.3

--

--

s

HIGH Period of the SCL Clock

0.6

--

--

s

Set-Up Time for a Repeated

START Condition

0.6

--

--

s

Data Hold Time

0

--

0.9

s

Data Set-Up Time

100

--

--

ns

Set-Up Time for STOP

Condition

0.6

--

--

s

Bus Free Time between a

STOP and START Condition

1.3

--

--

s

Rising Time of both SDA and

SCL Signals

20

--

300

ns

Falling Time of both SDA and

SCL Signals

20

--

300

ns

SDA and SCL Output Low Sink

Current

SDA or SCL Voltage = 0.4V

2

--

--

mA

I