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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DM505LRBABF bảng dữ liệu(PDF) 13 Page - Texas Instruments |
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DM505LRBABF bảng dữ liệu(HTML) 13 Page - Texas Instruments |
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13 / 290 page  Copyright © 2016–2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback 13 DM505 www.ti.com SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 Table 4-1. Pin Attributes(1) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] BALL RESET REL. MUXMODE [8] I/O VOLTAGE VALUE [9] POWER [10] HYS [11] BUFFER TYPE [12] PULL UP/DOWN TYPE [13] DSIS [14] R2 ddr1_a14 ddr1_a14 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy V1 ddr1_a15 ddr1_a15 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy B3 ddr1_ba0 ddr1_ba0 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy A3 ddr1_ba1 ddr1_ba1 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy D2 ddr1_ba2 ddr1_ba2 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy F3 ddr1_cke0 ddr1_cke0 0 O PD drive 0 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy B2 ddr1_csn0 ddr1_csn0 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy AA6 ddr1_d0 ddr1_d0 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA8 ddr1_d1 ddr1_d1 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y8 ddr1_d2 ddr1_d2 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA7 ddr1_d3 ddr1_d3 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AB4 ddr1_d4 ddr1_d4 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y5 ddr1_d5 ddr1_d5 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA4 ddr1_d6 ddr1_d6 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y6 ddr1_d7 ddr1_d7 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA18 ddr1_d8 ddr1_d8 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy Y21 ddr1_d9 ddr1_d9 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AA21 ddr1_d10 ddr1_d10 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy Y22 ddr1_d11 ddr1_d11 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AA19 ddr1_d12 ddr1_d12 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AB20 ddr1_d13 ddr1_d13 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy Y17 ddr1_d14 ddr1_d14 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AB18 ddr1_d15 ddr1_d15 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy |
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