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DM505LRBABF bảng dữ liệu(PDF) 84 Page - Texas Instruments |
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DM505LRBABF bảng dữ liệu(HTML) 84 Page - Texas Instruments |
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84 / 290 page  84 DM505 SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-5. Maximum Supported Frequency (continued) Module Clock Sources Instance Name Input Clock Name Clock Type Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name PLL / OSC / Source Name GMAC_SW CPTS_RFT_CLK Func 266 GMAC_RFT_CLK L3_ICLK DPLL_CORE SYS_CLK1 OSC0 MAIN_CLK Int 125 GMAC_MAIN_CLK GMAC_250M_CLK DPLL_GMAC MHZ_250_CLK Func 250 GMII_250MHZ_CL K GMII_250MHZ_CL K DPLL_GMAC MHZ_5_CLK Func 5 RGMII_5MHZ_CLK RGMII_5MHZ_CLK RMII_CLK MHZ_50_CLK Func 50 RMII_50MHZ_CLK GMAC_RMII_HS_ CLK DPLL_GMAC GPIO1 GPIO1_ICLK Int 38.4 WKUPAON_GICL K SYS_CLK1 OSC0 GPIO1_DBCLK Func 0.032 WKUPAON_SYS_ GFCLK WKUPAON_32K_ GFCLK OSC0 GPIO2 GPIO2_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE GPIO2_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0 GPIO3 GPIO3_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE GPIO3_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0 GPIO4 GPIO4_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE GPIO4_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0 GPMC GPMC_ICLK Int 266 L3MAIN1_L3_GIC LK CORE_X2_CLK DPLL_CORE I2C1 I2C1_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE I2C1_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER I2C2 I2C2_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE I2C2_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER IEEE1500_2_OC P PI_L3CLK Int & Func 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE IPU1 IPU1_GFCLK Int & Func IPU_CLK IPU1_GFCLK SYS_CLK1 OSC0 CORE_IPU_ISS_B OOST_CLK DPLL_CORE L3_INSTR L3_CLK Int L3_CLK L3INSTR_L3_GICL K CORE_X2_CLK DPLL_CORE L4_CFG L4_CFG_CLK Int 133 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE L4_PER1 L4_PER1_CLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE L4_PER2 L4_PER2_CLK Int 133 L4PER2_L3_GICL K CORE_X2_CLK DPLL_CORE L4_PER3 L4_PER3_CLK Int 133 L4PER3_L3_GICL K CORE_X2_CLK DPLL_CORE L4_WKUP L4_WKUP_CLK Int 38.4 WKUPAON_GICL K SYS_CLK1 OSC0 MAILBOX1 MAILBOX1_FLCK Int 133 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE MAILBOX2 MAILBOX2_FLCK Int 133 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE |
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