8XC552 datasheet(2/60 Pages) PHILIPS

2 / 60 page

Philips Semiconductors

80C51 Family Derivatives

8XC552/562 overview

1996 Aug 06

8XC552 OVERVIEW

The 8XC552 is a stand-alone high-performance microcontroller

designed for use in real-time applications such as instrumentation,

industrial control, and automotive control applications such as

engine management and transmission control. The device provides,

in addition to the 80C51 standard functions, a number of dedicated

hardware functions for these applications.

The 8XC552 single-chip 8-bit microcontroller is manufactured in an

advanced CMOS process and is a derivative of the 80C51

microcontroller family. The 8XC552 uses the powerful instruction set

of the 80C51. Additional special function registers are incorporated

to control the on-chip peripherals. Three versions of the derivative

exist although the generic term “8XC552” is used to refer to family

members:

83C552: 8k bytes mask-programmable ROM, 256 bytes RAM

87C552: 8k bytes EPROM, 256 bytes RAM

80C552: ROMless version of the 83C552

The 8XC552 contains a nonvolatile 8k

× 8 read-only program

memory, a volatile 256

× 8 read/write data memory, five 8-bit I/O

ports and one 8-bit input port, two 16-bit timer/event counters

(identical to the timers of the 80C51), an additional 16-bit timer

coupled to capture and compare latches, a fifteen-source,

two-priority-level, nested interrupt structure, an 8-input ADC, a dual

DAC pulse width modulated interface, two serial interfaces (UART

and I2C bus), a “watchdog” timer, and on-chip oscillator and timing

circuits. For systems that require extra capability, the 8XC552 can

be expanded using standard TTL compatible memories and logic

The 8XC552 has two software selectable modes of reduced activity

for further power reduction—Idle and Power-down. The idle mode

freezes the CPU and resets Timer T2 and the ADC and PWM

circuitry but allows the other timers, RAM, serial ports, and interrupt

system to continue functioning. The power-down mode saves the

RAM contents but freezes the oscillator, causing all other chip

functions to become inoperative.

83C562 OVERVIEW

The 83C562 has been derived from the 8XC552 with the following

changes:

• The SIO1 (I2C) interface has been omitted.

• The output of port lines P1.6 and P1.7 have a standard

configuration instead of open drain.

• The resolution of the A/D converter is decreased from 10 bits to 8

bits.

• The time of an A/D conversion has decreased from 50 machine

cycles to 24 machine cycles.

All other functions, pinning and packaging are unchanged.

This chapter of the users’ guide can be used for the 83C562 by

omitting or changing the following:

• Disregard the description of SIO1 (I2C).

• The SFRs for the interface: S1ADR, S1DAT, S1STA, and S1CON

are not implemented. The two SIO1 related flags ES1 in SFR

IEN0 and PS1 in SFR IP0 are also not implemented. These two

flag locations are undefined after RESET. The interrupt vector for

SIO1 is not used.

• Port lines P1.6 and P1.7 are not open drain but have the same

standard configuration and electrical characteristics as P1.0-P1.5.

Port lines P1.6 and P1.7 have alternative functions.

• The A/D converter has a resolution of 8 bits instead of 10 bits and

consequently the two high-order bits 6 and 7 of SFR ADCON are

not implemented. These two locations are undefined after RESET.

The 8-bit result of an A/D conversion is present in SFR ADCH.

The result can always be calculated from the formula:

256

IN * AVref

ref

) * AVref*

The A/D conversion time is 24 machine cycles instead of 50

machine cycles, and the sampling time is 6 machine cycles

instead of 8 machine cycles. The conversion time takes 3

machine cycles per bit.

• The serial I/O function SIO0 and its SFRs S0BUF and S0CON are

renamed to SIO, SBUF, and SCON. The interrupt related flags

ES0 and PS0 are renamed ES and PS. Interrupt source S0 is

renamed S. The serial I/O function remains the same.

Differences From the 80C51

Program Memory

The 8XC552 contains 8k bytes of on-chip program memory which

can be extended to 64k bytes with external memories (see

Figure 1). When the EA pin is held high, the 8XC552 fetches

instructions from internal ROM unless the address exceeds 1FFFH.

Locations 2000H to FFFFH are fetched from external program

memory. When the EA pin is held low, all instruction fetches are

from external memory. ROM locations 0003H to 0073H are used by

interrupt service routines.

Data Memory

The internal data memory is divided into 3 sections: the lower 128

bytes of RAM, the upper 128 bytes of RAM, and the 128-byte

special function register areas. The lower 128 bytes of RAM are

directly and indirectly addressable. While RAM locations 128 to 255

and the special function register area share the same address

space, they are accessed through different addressing modes. RAM

locations 128 to 255 are only indirectly addressable, and the special

function registers are only directly addressable. All other aspects of

the internal RAM are identical to the 8051.

The stack may be located anywhere in the internal RAM by loading

the 8-bit stack pointer. Stack depth is 256 bytes maximum.

Special Function Registers

The special function registers (directly addressable only) contain all

of the 8XC552 registers except the program counter and the four

control the on-chip peripheral hardware. Other registers include

arithmetic registers (ACC, B, PSW), stack pointer (SP), and data

pointer registers (DHP, DPL). Sixteen of the SFRs contain 128

directly addressable bit locations. Table 1 lists the 8XC552’s special

function registers.

The standard 80C51 SFRs are present and function identically in the

8XC552 except where noted in the following sections.

8XC552 bảng dữ liệu(PDF) 2 Page - NXP Semiconductors

8XC552 bảng dữ liệu(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

bảng dữ liệu tải về

Link URL