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S5D9 bảng dữ liệu(PDF) 91 Page - Renesas Technology Corp |
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S5D9 bảng dữ liệu(HTML) 91 Page - Renesas Technology Corp |
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91 / 115 page  R01DS0303EU0100 Rev.1.00 Page 91 of 115 Nov 3, 2016 S5D9 2. Electrical Characteristics Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during A/D conversion, values might not fall within the indicated ranges. The use of pins AN000 to AN007 as digital outputs is not allowed when the 12-Bit A/D converter is used. The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage is stable. Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test conditions. Note 2. Values in parentheses indicate the sampling time. High-precision channels (AN003 to AN007) Conversion time*1 (operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.48 (0.267)*2 -- μs Sampling in 16 states Max. = 400 Ω 0.40 (0.183)*2 -- μs Sampling in 11 states VCC = AVCC0 = 3.0 to 3.6 V 3.0 V ≤ VREFH0 ≤ AVCC0 Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - Normal-precision channels (AN016 to AN020) Conversion time*1 (Operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.88 (0.667)*2 -- μs Sampling in 40 states Offset error - ±1.0 ±5.5 LSB - Full-scale error - ±1.0 ±5.5 LSB - Absolute accuracy - ±2.0 ±7.5 LSB - DNL differential nonlinearity error - ±0.5 ±4.5 LSB - INL integral nonlinearity error - ±1.0 ±5.5 LSB - Table 2.41 A/D conversion characteristics for unit 1 (1 of 2) Conditions: PCLKC = 1 to 60 MHz Item Min Typ Max Unit Test conditions Frequency 1 - 60 MHz - Analog input capacitance - - 30 pF - Quantization error - ±0.5 - LSB - Resolution - - 12 Bits - Channel-dedicated sample-and-hold circuits in use (AN100 to AN102) Conversion time*1 (operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 1.06 (0.4 + 0.25)*2 -- μs Sampling of channel- dedicated sample-and-hold circuits in 24 states Sampling in 15 states Offset error - ±1.5 ±3.5 LSB AN100 to AN102 = 0.25 V Full-scale error - ±1.5 ±3.5 LSB AN100 to AN102 = VREFH - 0.25 V Absolute accuracy - ±2.5 ±5.5 LSB - DNL differential nonlinearity error - ±1.0 ±2.0 LSB - INL integral nonlinearity error - ±1.5 ±3.0 LSB - Holding characteristics of sample-and hold circuits -- 20 μs- Dynamic range 0.25 - VREFH - 0.25 V- Table 2.40 A/D conversion characteristics for unit 0 (2 of 2) Conditions: PCLKC = 1 to 60 MHz Item Min Typ Max Unit Test conditions |
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