S5D9 datasheet(59/115 Pages) RENESAS

59 / 115 page

R01DS0303EU0100 Rev.1.00

Page 59 of 115

Nov 3, 2016

S5D9

2. Electrical Characteristics

Figure 2.29

SDRAM self-refresh timing

2.3.7

I/O Ports, POEG, GPT32, AGT, KINT, and ADC12 Trigger Timing

Table 2.19

I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (1 of 2)

GPT32 Conditions:

High drive output is selected in the port drive capability bit in the PmnPFS register.

AGT Conditions:

Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Item

Symbol Min

Max

Unit

Test

conditions

I/O ports

Input data pulse width

tPRW

1.5

tPcyc

Figure 2.30

POEG

POEG input trigger pulse width

tPOEW

tPcyc

Figure 2.31

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

A15 to A00

(RFS)

SDCLK

SDCS

AP*1

DQMn

DQ15 to DQ00

RAS

CAS

CKE

(Hi-Z)

tCKED

(High)

tCASD

tRASD tRASD

tRASD

t CSD2

tCSD2

t CSD2

t AD2

(RFA)

(RFX)

(RFA)

t AD2

t CSD2

tCSD2

tRASD

tRASD tRASD tRASD

tCASD

tCASD tCASD tCASD

tCKED

SDRAM command

t DQMD

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