HT69F240 datasheet(49/172 Pages) HOLTEK

49 / 172 page

Rev. 1.20

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Rev. 1.20

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HT69F240

I/O 8-Bit Flash MCU with LED/LCD Driver

HT69F240

I/O 8-Bit Flash MCU with LED/LCD Driver

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistouse

thesingle"CLRWDT"instructiontocleartheWDTcontents.

Themaximumtimeoutperiodiswhenthe218divisionratioisselected.Asanexample,witha

32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8

secondforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

“

CLR WDT”Inst�u�tion

8-stage Divide�

WDT P�es�ale�

WE4~WE0 bits

WDTC Registe�

Reset �CU

LXT

fSUB

fSUB/28

8-to-1 �UX

CLR

WS2~WS0

(fSUB/28 ~ fSUB/218)

WDT Time-out

(28/fSUB ~ 218/fSUB)

LIRC

�

Low Speed Os�illato�

Configu�ation option

“

HALT”Inst�u�tion

Watchdog Timer

Reset and Initialisation

Aresetfunctionisafundamentalpartofanymicrocontrollerensuringthatthedevicecanbeset

tosomepredeterminedconditionirrespectiveofoutsideparameters.Themostimportantreset

conditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase,internalcircuitrywill

ensurethatthemicrocontroller,afterashortdelay,willbeinawelldefinedstateandreadyto

executethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisters

willbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgram

Counter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthe

lowestProgramMemoryaddress.

AnothertypeofresetiswhentheWatchdogTimeroverflowsandresetstheMCU.Alltypesofreset

operationsresultindifferentregisterconditionsbeingsetup.Anotherresetexistsintheformofa

LowVoltageReset,LVR,whereafullreset,isimplementedinsituationswherethepowersupply

voltagefallsbelowacertainthreshold.

Reset Functions

Therearefourwaysinwhicharesetcanoccur.

Power-on Reset

Themostfundamentalandunavoidableresetistheonethatoccursafterpowerisfirstappliedtothe.

AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,a

power-onresetalsoensuresthatcertainotherregistersarepresettoknownconditions.AlltheI/O

portandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstset

toinputs.

VD D

In te r nal R es et

t RS TD + t SST

Power-On Reset Timing Chart

Note:tRSTDispower-ondelay,typicaltime=50ms

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