SPEAR600 datasheet(9/97 Pages) STMICROELECTRONICS

9 / 97 page

SPEAr600

Description

Doc ID 16259 Rev 3

9/97

1.1

Main features

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Dual core ARM926EJ-S 32-bit RISC CPU, up to 333 MHz, each with:

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16 Kbytes of instruction cache, 16 Kbytes of data cache

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3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code

density, byte Java mode (Jazelle™) for direct execution of Java code.

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Tightly Coupled Memory

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AMBA bus interface

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32-KByte on-chip BootROM

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8-KByte on-chip SRAM

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Dynamic memory controller managing external DDR1 memory up to 166 MHz and

external DDR2 memory up to 333 MHz

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Serial memory interface

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8/16-bits NAND Flash controller

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Possible NAND Flash or serial NOR flash booting

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Multichannel DMA controller

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Color LCD Controller for STN/TFT display panels

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Up to 1024 x 768 resolution

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24 bpp true color

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Ethernet GMAC 10/100/1000 Mbps (GMII/MII PHY interface)

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Two USB 2.0 host (high-full-low speed) with integrated PHY transceiver

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One USB 2.0 device (high-full speed) with integrated PHY transceiver

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10 GPIO bidirectional signals with interrupt capability

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JPEG codec accelerator 1clock/pixel

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ADC 10-bit, 1 Msps 8 inputs/1-bit DAC

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3 SSP master/slave (supporting Motorola, Texas instruments, National Semiconductor

protocols) up to 40 Mbps

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I2C master/slave interface (slow/ fast/high speed, up to 1.2 Mb/s)

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10 independent 16-bit timers with programmable prescaler

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I/O peripherals

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Two UARTs (speed rate up to 460.8 kbps)

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Fast IrDA (FIR/MIR/SIR) 9.6 Kbps to 4 Mbps speed-rate

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Audio block with 3-I2Ss interfaces to support Audio Play (Up to 3.1) and Audio Record

functionality.

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Advanced power saving features

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Normal, Slow, Doze and Sleep modes, CPU clock with software-programmable

frequency

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Enhanced dynamic power-domain management

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Clock gating functionality

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Low frequency operating mode

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Automatic power saving controlled from application activity demands

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Vectored interrupt controller

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System and peripheral controller

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