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AD7183 bảng dữ liệu(PDF) 30 Page - Analog Devices

tên linh kiện AD7183
Giải thích chi tiết về linh kiện  Advanced Video Decoder with 10-Bit ADC and Component Input Support
PDF  40 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
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AD7183 bảng dữ liệu(HTML) 30 Page - Analog Devices

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ADV7183
Table XXXII. Pixel Delay Control Register (Subaddress 27)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
RESERVED
0
0
0
Set to Zero
CTA[2:0]
1
0
0
0
Not Valid
0
0
1
Chroma + 2 Pixel (Early)
0
1
0
Chroma + 1 Pixel (Early)
0
1
1
No Delay
1
0
0
Chroma – 1 Pixel (Late)
1
0
1
Chroma – 2 Pixel (Late)
1
1
0
Chroma – 3 Pixel (Late)
1
1
1
Not Valid
RESERVED
1
Set to One
SWPC
2
0
No Swapping
1
Swap the Cr and Cb Values
NOTES
1Chroma Timing Adjust. Allows a specified timing difference between the luma and chroma samples.
2Allows the Cr and Cb samples to be swapped.
Table XXXIII. Manual Clock Control 1 Register (Subaddress 28)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
CLKVAL[17:16]
1
XX
RESERVED
1111
Set to Default
CLKMANE
2
0
Output Frequency Set by Video
1
Frequency Set by CLKVAL[17:0]
FIX27E
3
0
Output Frequency Set by Clock Generator
1
Output 27 MHz Fixed
NOTES
1If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins.
2Clock Generator Manual Enable. Allows the analog clock generator to produce a fixed clock frequency that is not dependent on the video signal.
3Allows the o/p of fixed 27 MHz crystal clock via LLC, LLC2, and LLCR EF o/p pins.
Table XXXIV. Manual Clock Control 2 Register (Subaddress 29)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
CLKVAL[15:8]
* XXXXXXXX
*If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins.
Table XXXV. Manual Clock Control 3 Register (Subaddress 2A)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
CLKVAL[7:0]
*
XXXXXXXX
*If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins.



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