AD7183 datasheet(17/40 Pages) AD

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REV. 0

ADV7183

–17–

Control and Pixel Interface FIFO Modes

When the ADV7183 is configured to operate in this mode, pixel

data generated within the part is buffered by a 512-pixel deep

FIFO. Only active video pixels and control codes are written into

the FIFO; the others have been dropped. In this mode the output

is operating asynchronously and a CLKIN must be provided to

clock pixels out of the FIFO. The CLKIN must operate faster than

the effective data transfer rate into the FIFO. This rate will be

determined by the number of active pixels per line. If the CLKIN

is not above this, the FIFO may overflow. The ADV7183 controls

the FIFO when set to operate in SCAPI mode. DV (data valid) is

internally fed back to the RD (read enable), unlike the synchronous

pixel mode where DV will not indicate the validity of the current

pixel and only acts as an indication of how much data is stored in

the FIFO. DV will go high at the same time as AFF and remain

high until the FIFO is empty.

By internally setting DV to RD the system ensures that the FIFO

never overflows. When using this mode the status of data on the

pixel outputs can be determined by two indicators, DV and QCLK.

DV will go active two clock cycles (LLC1) before valid data appears

on the bus. QCLK is a qualified clock derived from CLKIN, but

will only be present when valid pixel data is output from the FIFO.

DV indicates valid pixel or control code data. Using these two

control signals, the user can differentiate between pixel information

and invalid data. Figure 25 shows the basic timing relationship

for this mode.

The operation of the ADV7183 in CAPI mode is similar to that

of SCAPI mode with the exception that now the FIFO is con-

trolled by the system; the system must monitor the almost full

flag (AFF), the almost empty flag (AEF), and control the FIFO

read enable (RD). Unlike SCAPI mode, the QCLK is not gated

and is therefore continuous. Figure 26 shows the basic timing

relationship of this mode.

PIXEL DATA

CLKIN

QCLK

AFF

AEF

NOTE

THE POLARITY OF AFF AND AEF ARE CONTROLLED BY THE PFF BIT.

DV POLARITY IS SET BY THE PDV BIT.

Figure 25. SCAPI Output Mode FIFO Operation

CLKIN

QCLK

AFF

AEF

NOTE

THE POLARITY OF AFF AND AEF ARE CONTROLLED BY THE PFF BIT.

DATA

Figure 26. CAPI Output Mode FIFO Operation

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