AD8331 datasheet(25/32 Pages) AD

25 / 32 page

AD8331/AD8332

Rev. C | Page 25 of 32

LO GAIN

MODE

15mV

–4.5

25mV

X-AMP

OVERLOAD

POSTAMP

OVERLOAD

X-AMP

OVERLOAD

POSTAMP

OVERLOAD

29dB

43.5

INPUT AMPLITUDE (V)

.275

0.1

10m

24.5dB

HI GAIN

MODE

4mV

7.5

25mV

41dB

56.5

INPUT AMPLITUDE (V)

24.5dB

0.275

0.1

10m

Figure 72. Overload Gain and Signal Conditions

The previously mentioned clamp interface controls the

maximum output swing of the postamp and its overload

response. When no RCLMP resistor is provided, this level defaults

to near 4.5 V p-p differential to protect outputs centered at a

2.5 V common mode. When other common-mode levels are set

through the VCM pin, the value of RCLMP should be chosen for

graceful overload. A value of 8.3 kΩ or less is recommended for

1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode).

This limits the output swing to just above 2 V p-p diff.

OPTIONAL INPUT OVERLOAD PROTECTION.

Applications in which high transients are applied to the LNA

input may benefit from the use of clamp diodes. A pair of back-

to-back Schottky diodes can reduce these transients to

manageable levels. Figure 73 illustrates how such a diode-

protection scheme may be connected.

LON

VPS

INH

COMM

ENBL

0.1

µF

BAS40-04

OPTIONAL

SCHOTTKY

OVERLOAD

CLAMP

Figure 73. Input Overload Clamping

When selecting overload protection, the important parameters

are forward and reverse voltages and trr (or τrr.). The Infineon

BAS40 series shown in Figure 73 has a τrr of 100 ps and VF of

310 mV at 1 mA. Many variations of these specifications can be

found in vendor catalogs.

LAYOUT, GROUNDING, AND BYPASSING

Due to their excellent high frequency characteristics, these

devices are sensitive to their PCB environment. Realizing

expected performance requires attention to detail critical to

good high speed board design.

A multilayer board with power and ground plane is

recommended, and unused area in the signal layers should be

filled with ground. The multiple power and ground pins provide

robust power distribution to the device and must all be

connected. The power supply pins should each be with multiple

values of high frequency ceramic chip capacitors to maintain

low impedance paths to ground over a wide frequency range.

These should have capacitance values of 0.01 μF to 0.1 μF in

parallel with 100 pF to 1 nF, and be placed as close as possible to

the pins. The LNA power pins should be decoupled from the

VGA using ferrite beads. Together with the decoupling

capacitors, ferrite beads help eliminate undesired high

frequencies without reducing the headroom, as do small value

resistors.

Several critical LNA areas require special care. The LON and

LOP output traces must be as short as possible before

connecting to the coupling capacitors connected to Pins VIN

and VIP. RFB must be placed nearby the LON pin as well.

Resistors must be placed as close as possible to the VGA output

pins VOL and VOH to mitigate loading effects of connecting

traces. Values are discussed in the section entitled Output

Filtering and Series Resistor

Requirements.

Signal traces must be short and direct to avoid parasitic effects.

Wherever there are complementary signals, symmetrical layout

should be employed to maintain waveform balance. PCB traces

should be kept adjacent when running differential signals over a

long distance.

MULTIPLE INPUT MATCHING

Matching of multiple sources with dissimilar impedances can

be accomplished as shown in the circuit of Figure 75. A relay

and low supply voltage analog switch may be used to select

between multiple sources and their associated feedback

resistors. An ADG736 dual SPDT switch is shown in this

example; however, multiple switches are also available and users

are referred to the Analog Devices Selection Guide for switches

and multiplexers.

DISABLING THE LNA

Where accessible, connection of the LNA enable pin to ground

will power down the LNA, resulting in a current reduction of

about half. In this mode, the LNA input and output pins may be

left unconnected, however the power must be connected to all

the supply pins for the disabling circuit to function. Figure 74

illustrates the connections using an AD8331 as an example.

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