AD9286

Data Sheet

Rev. C | Page 8 of 27

CLK+

CLK–

DCO+, DCO–

DATA

AUXCLK+

AUXCLK–

N – 1

N – 2

N + 1

N + 2

N + 4

N + 3

N

VIN1+, VIN1–

VIN2+, VIN2–

M – 1

M + 1

M + 5

M + 4

M + 3

M + 2

M

N – 11

M – 11

M – 10

N – 10

M – 9

N – 9

M – 8

M – 7

N – 8

Figure 5. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 1, CLK and AUXCLK Out of Phase