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L9634

Figure 13. Arming Shift Register

4.5

ARM23 / ARMEN

In discrete mode, this pin acts as the ARM input channel 2 and channel 3. In serial mode, this pin acts as

an active high input to select this device for serial transfers. This pin has a TTL level compatible input volt-

ages allowing proper operation with another devices using a 3.3V to 5.0V supply.

While ARMEN is asserted, arming register data is shifted into the ARMIN pin and shifted-out of the AR-

MOUT pin on both rising and falling edges of ARMCLK. On the falling edge of ARMEN, OSD latch-in the

bits from the shift register, and clear the shift register contents.

4.6

ARM45 / ARMCLK

In discrete mode, this pin acts as the ARM input channel 4 and channel 5. In serial mode, this pin acts as

a clock input for serial communication. This pin has a TTL level compatible input voltages allowing proper

operation with another devices using a 3.3V to 5.0V supply.

When ARMEN is asserted, on the rising or falling edge of ARMCLK the logic level input at the ARMIN pin

is shifted into the internal Arming shift register. While MSB in the shift register is shifted-out on the AR-

MOUT pin. Serial data is shifted in and out of the shift register on each ARMCLK edge. When ARMEN is

negated, OSD ignores ARMCLK signal.

A clock edge counter is provided to verify a valid serial arming communication. A valid serial arming com-

munication contains (4n - 1) ARMCLK edges. Otherwise, OSD ignores the serial arming messages.

4.7

ARM67 / ARMOUT

In discrete mode, this pin acts as the ARM input channel 6 and channel 7. In serial mode, this pin acts as

the output of Arming shift register. This pin has a TTL level compatible input voltages allowing proper op-

eration with another devices using a 3.3V to 5.0V supply.

When ARMEN is negated, ARMOUT pin is pulled down. When ARMEN is asserted, the MSB is the first

bit of the nibble shifted onto ARMOUT. The LSB is the last bit shifted onto ARMOUT.

4.8

TEST / DEPEN (Deployment Enable)

DEPEN is a deployment enable input, which is an active high input. When DEPEN is negated, it inhibits

the high-side and the low-side MOSs from turning on. If DEPEN is negated when a valid deployment is

received, OSD inhibits the deployment. If DEPEN is negated when a diagnostic command is received,

OSD executes the diagnostic sequence. If a MOS diagnostic is executed while DEPEN is negated, OSD

returns a low-side MOS fault. SPI remains functional while this pin is pulled low. When this pin is asserted,

OSD is able to drive its high and low side drivers upon receiving a valid deployment command or a MOS

diagnostic. DEPEN does not initiate a deployment nor terminate a deployment if it is already started.

To enter a test mode, this pin has to be pulled higher than VIH_TEST.

4.9

Deployment Driver Diagnostics

OSD runs an on-chip self-diagnostics when commanded via SPI. By default, OSD is in the monitor mode

(D15 & D14 = %11). The on-chip diagnostic operates according to the flow chart shown in Figure 15. If a

fault condition is detected, the state machine asserts a fault bit, which serves as a flag to the processor.

Once a fault bit asserted, OSD terminates the diagnostic tests for that particular channel and start diag-

nostic tests on the next channel. The fault information in OSD is sent out through MISO. For diagnostic

ARM67

ARM01

ARM23

ARM45

MSB

LSB

14

3

2

Obsolete

Product(s)

- Obsolete

Product(s)