Three-Wire True Zero-Speed Differential Peak-Detecting

Sensor IC with Continuous Calibration

ATS468

9

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Automatic Gain Control (AGC)

This feature allows the device to operate with an optimal internal

electrical signal, regardless of the differential signal amplitude

tion, the device determines the peak-to-peak amplitude of the

signal generated by the target. The gain of the device is then auto-

matically adjusted. Figure 4 illustrates the effect of this feature.

During running mode, the AGC continues to monitor the system

amplitude, reducing the gain if necessary; see the Device Opera-

tion section for more details.

Automatic Offset Adjust (AOA)

The AOA is patented circuitry that automatically compensates for

the effects of chip, magnet, and installation offsets. This circuitry

is continuously active, including both during calibration mode

and running mode, compensating for offset drift. Continuous

operation also allows it to compensate for offsets induced by

temperature variations over time.

Digital Peak Detection

and is used for holding the peak value of the internal analog

signal. In the example shown in Figure 5, the DAC would first

track up with the signal and hold the upper peak’s value. When

esis, the output would switch and the DAC would begin tracking

DAC acquires the negative peak, the output will again switch

this point, the DAC tracks up again and the cycle repeats. The

digital tracking of the differential analog signal allows the device

to achieve true zero-speed operation.

Figure 4: Automatic Gain Control (AGC)

The AGC function corrects for variances in the air gap. Differences in

the air gap affect the magnetic gradient, but AGC prevents that from

affecting device performance, as shown in the lowest panel.

N

N

S

S

Target

Ring Magnet

Internal Differential

Analog Signal

Response, with AGC

Internal Differential

Analog Signal

Response, without AGC

V+

V+

Internal

Differential

Analog Signal,

Device Output,

V–

0

V+

Figure 5: The Peaks in the Resulting Differential Signal

Switchpoints.

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