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DFE252012C bảng dữ liệu(PDF) 10 Page - MagnaChip Semiconductor.

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Giải thích chi tiết về linh kiện  Dual Output LCD Bias IC
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Confidential
Datasheet Version 1.1
Mar. 2015. Revision 1.1
MagnaChip Semiconductor Ltd.
10
Applications
Under-voltage Lockout
If the input voltage falls below the VUVLO level of 2.1V, all the DC/DC regulators of MAP7102 are disabled, and
all the rails will restart with soft-start when input voltage is applied again
ENP/ENN
The ENP pin controls the output of VPOS and the ENN pin controls the output of VNEG. A high on either ENP
or ENN will enable the boost converter VREG. VPOS, VNEG and VREG require both their respective EN pin high
for each to be enabled
Power On / Off Sequence
The VREG boost regulator is activated when the input voltage is higher than the UVLO threshold, and either ENP
or ENN are high. The VPOS output is activated if ENP is high and VREG has completed its soft-start. The VNEG
output is activated if ENN is high and VREG has completed its soft-start.
ENP or ENN being pulled low shuts down VPOS or VNEG, respectively. If both ENP and ENN are pulled low,
VPOS, VNEG and VREG are all turned off
The discharge resistors of the VPOS and VNEG output are 70
Ω and 20Ω respectively.
VIN
ENP
ENN
VREG
VREG power good
VPOS
VNEG
UVLO
0.7ms
0.7ms
0.7ms
VIN
ENP
ENN
VREG
VREG power good
VPOS
VNEG
UVLO
0.7ms
0.7ms
0.7ms
Figure 18: Example of power on sequence when ENN
Figure 19: Example of power on sequence when both ENP
rising after VPOS soft-start finished
and ENN rising before VREG soft-start finished



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