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Z86L02 bảng dữ liệu(PDF) 26 Page - Zilog, Inc.

tên linh kiện Z86L02
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Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8® Microcontrollers
Zilog
26
P R E L I M I N A R Y
DS96DZ80301
FUNCTIONAL DESCRIPTION (Continued)
Internal Address Counter. The address of Z86E02 is
generated internally with a counter clocked through pin
P01 (Clock). Each clock signal increases the address by
one and the "high" level of pin P00 (Clear) will reset the ad-
dress to zero. Figure 19 shows the setup time of the serial
address input.
Programming Waveform. Figures 20, 21, 22, and 23
show the programming waveforms of each mode. Table 7
shows the timing of programming waveforms.
Programming Algorithm. Figure 24 shows the flow chart
of the Z86E02 programming algorithm.
Table 6. EPROM Programming Table
Programming
Modes
VPP
EPM
/CE
/OE
/PGM
ADDR
DATA
VCC*
EPROM READ
NU
VH
VIL
VIL
VIH
ADDR
Out
5.0V
PROGRAM
VH
VIH
VIL
VIH
VIL
ADDR
In
6.4V
PROGRAM VERIFY
VH
VIH
VIL
VIL
VIH
ADDR
Out
6.4V
ROM PROTECT
VH
VH
VH
VIH
VIL
NU
NU
5.0-6.4V
LOW NOISE
SELECT
VH
VIH
VH
VIH
VIL
NU
NU
5.0-6.4V
AUTO LATCH
DISABLE
VH
VIH
VH
VIL
VIL
NU
NU
5.0-6.4V
WDT ENABLE
VH
VIL
VH
VIH
VIL
NU
NU
5.0-6.4V
EPROM/TEST
MODE Disable
VH
VIL
VH
VIL
VIL
NU
NU
5.0-6.4V
Notes: VH=13.0V ±0.25 VDC.
VIH=As per specific Z8 DC specification.
VIL=As per specific Z8 DC specification.
X=Not used, but must be set to VH, VIH, or VIL level.
NU=Not used, but must be set to either VIH or VIL level.
IPP during programming = 40 mA maximum.
ICC during programming, verify, or read = 40 mA maximum.
* VCC has a tolerance of ±0.25V.
Table 7. Z86E02 Timing of Programming Waveforms
Parameters
Name
Min
Max
Units
1
Address Setup Time
2
µs
2
Data Setup Time
2
µs
3VPP Setup
2
µs
4VCC Setup Time
2
µs
5
Chip Enable Setup Time
2
µs
6
Program Pulse Width
0.95
ms
7
Data Hold Time
2
µs
8
/OE Setup Time
2
µs
9
Data Access Time
188
4000
ns
10
Data Output Float Time
100
ns
11
Over-program Pulse Width
2.85
3.2
ms
12
EPM Setup Time
2
µs
13
/PGM Setup Time
2
µs
14
Address to /OE Setup Time
2
µs
15
Option Program Pulse Width
150
ms
16
/OE Low Width
250
ns



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