TPS720

www.ti.com

SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015

Feature Description (continued)

mA. The inrush current charges the LDO output capacitor. If the output of the LDO regulates to 1.3 V, then the

LDO charges the output capacitor to the final output value in approximately 28.6

μs.

Another consideration is when a load is connected to the output of an LDO. The connected load tries to steer a

7.3.3 Shutdown

The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When

shutdown capability is not required, EN can be connected to the IN pin.

7.3.4 Undervoltage Lockout (UVLO)

The TPS720 uses an undervoltage lock-out circuit on the BIAS pin to keep the output shut off until the internal

circuitry is operating properly. The UVLO circuit has a deglitch feature so that it typically ignores undershoot

transients on the input if they are less than 50-

μs duration.

7.4 Device Functional Modes

Driving the EN pin over 1.1 V turns on the regulator. Driving the EN pin below 0.4 V causes the regulator to enter

shutdown mode. In shutdown, the current consumption of the device is reduced to 500 nA, typically.

Copyright © 2008–2015, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Links: TPS720